For some reason, I'm unable to use assertion statements in my SystemVerilog files:


module test_module( input  logic i_a,
                    output logic o_c );

    and m_gate_0(o_c, i_a, i_b);


module test_module_tb;
    logic l_a, l_b, l_c;

    test_module m_dut(  .i_a( l_a),
                        .i_b( l_b),
                        .o_c( l_c) );

    initial begin

        l_a = 1'b1;
        l_b = 1'b1;
        assert( l_c === 1'b1 );



$ iverilog -Wall -Winfloop -g2012 test_module_tb.sv \ test_module.sv -o test_module_tb
test_module_tb.sv:15: syntax error
test_module_tb.sv:15: error: malformed statement
test_module_tb.sv:15: sorry: Simple immediate assertion statements not implemented.

$ iverilog -v
Icarus Verilog version 10.3 (stable) ()

$ uname -r

Line 15 is this one: assert( l_c === 1'b1 );

I'm currently doing homework and the above code worked on the Uni's Raspberry Pi's but doesn't work on my Zorin 16.2 laptop. Perhaps some library responsible for assertions is missing?

What am I doing wrong?


1 Answer 1


You are not doing anything wrong. iverilog does not support all SystemVerilog syntax, and the version you are using tells you the assert syntax has not been implemented. There is no missing assertion library.

You have 2 choices: use a different simulator that supports the assertion syntax you want to use, or use some other syntax that is similar to assertions.

There are free simulators available on EDA Playground, such as Synopsys VCS, that support assert. You could check if there is a newer version of iverilog available, but there's no guarantee it will support assertions.

Or, you could avoid assertions if you want to stay with iverilog. For example, change:

  assert( l_c === 1'b0 );

to something like:

  if( l_c === 1'b0 ) ; else $error;

Working iverilog example on EDA Playground

  • \$\begingroup\$ Well, I was able to install iverilog version 12.0 following these instructions: geeksforgeeks.org/how-to-install-verilog-hdl-on-linux However, Version 12 is now only available in the verilog source folder but not outside of it (there, it's still version 10.3). Do you have any advice on how to make version 12 available globally? \$\endgroup\$
    – Pixelcode
    Nov 6, 2022 at 22:28
  • \$\begingroup\$ @Pixelcode: No, not really. However, since my answer provided a solution to your original question, you can go ahead and Accept it. \$\endgroup\$
    – toolic
    Nov 7, 2022 at 11:06
  • \$\begingroup\$ Ok, thank you :) \$\endgroup\$
    – Pixelcode
    Nov 13, 2022 at 1:40

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