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I'm looking for hardware that will take two physical I2S data lines, both clocked using the same WS and BCLK lines, and interlace each sample from them together to one output I2S line at double the clock speed.

Below is an example of what I'd like to do. For simplicity, this example shows only 4 bits/sample.

timing diagram example

Does hardware like this exist, or is this so specialized that this would be a job for an FPGA? Each sample is 16 bits/sample and at a high clock speed of 325 kHz samples/sec or a bit clock of 10.4 MHz.

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    \$\begingroup\$ But it would not be I2S any more. 2 channels is I2S, more than 2 channels is TDM. Even if you can merge 4 channels from two I2S channels into one four-channel TDM stream, no I2S interface can receive it. Unless you interleave the samples but then you can't know what you are receiving, will this left sample on wire be from I2S stream 1 or 2. Can you explain what you are trying to do as there may be better ways to solve it (X-Y problem)? \$\endgroup\$
    – Justme
    Commented Nov 7, 2022 at 21:12
  • \$\begingroup\$ @Justme Thanks for the reply. Each physical data line is carrying a mono channel and the WS line is just being used to break up each sample's bits, so I don't care if the WS is high or low on each input data line. What I'm using this to do is to send in IQ data, which can basically be thought of as two channel audio, to an MCU. The source for this IQ data is from a piece of dedicated hardware that will only output it using two data lines with a shared clock, one for each channel. \$\endgroup\$
    – RomanPort
    Commented Nov 7, 2022 at 21:34
  • \$\begingroup\$ Seems like simplest to use two I2S ports on a MCU than combine them separately. \$\endgroup\$
    – Justme
    Commented Nov 7, 2022 at 21:40
  • \$\begingroup\$ @Justme Thanks for the response. Unfortunately the STM32 I'm using does not guarantee that the two I2S inputs will always be clocked exactly the same and I need to make sure that the two channels are synchronized to each other. I also need to interlace each sample in software, which will consume a lot of CPU cycles. I would really much rather do it separately so I don't have to worry about it. \$\endgroup\$
    – RomanPort
    Commented Nov 7, 2022 at 22:46
  • \$\begingroup\$ Your diagram doesn't seem to make sense to me – WS needs to stay the same, only BCLK (and the actual bits) would double in speed, right? \$\endgroup\$ Commented Nov 7, 2022 at 23:49

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I'm sure there's some expensive and hard to program audio DSP chip meant to do exactly this, somewhen from when I²S was quite new and things like audio mixing would have been impossible in usual microcontrollers, and state-of-the-art PLAs would have been lacking in clocking options.

However, this looks like something that you'd simply solve using reconfigurable logic. It'd need a PLL, ideally, to synthesize the 2× BCLKin clock.

Does hardware like this exist, or is this so specialized that this would be a job for an FPGA?

Not very specialized, still a job for an FPGA. Just as you don't have a different hammer for every different size of nail, sometimes the one-size-fits all solution of reconfigurable logic that comes with a PLL: An FPGA.

I also need to interlace each sample in software, which will consume a lot of CPU cycles.

Really raises the question on whether I²S is the right format for high-speed IQ data.

Other than that, 8 bit of buffer are no problem on an FPGA – instead of bit-interleaving, what about channel-interleaving? Would make a lot more sense to me.

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  • \$\begingroup\$ Thanks for the response. I2S isn't ideal, but that's not something I have control over. The hardware I need to use only provides it in this format. I'm not bit-interleaving, I am interleaving one sample from each channel into the output almost like a zipper. Would you happen to have an FPGA you recommend? I'm having trouble finding anything simple enough for what I need that's in stock at the moment. \$\endgroup\$
    – RomanPort
    Commented Nov 14, 2022 at 21:20

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