Cannot perform a part select on array error

Question

I'm trying to read a file and use its data as inputs to my design. The file looks like this:

(1, 0, 0, 0) 
(0, 0, 0, 0) 
(0, 0, 0, 0) 
(0, 0, 0, 0)
(1, 1, 1, 1) 
(0, 0, 0, 0) 
(0, 0, 0, 0) 
(0, 0, 0, 0)
(513, 514, 515, 516) 
(513, 514, 515, 516) 
(513, 514, 515, 516) 
(513, 514, 515, 516)

These are supposed to be the outputs of an array. Each cell in the array generates 10 bits, but I need to send them serially. I want to send each column data serially to my design, which means each column is sending 40 bits in each cycle of testing. So the first column data in the file is for modeling the first column of the array in three test vectors. For the first test:

1 0 0 0 
0 0 0 0 
0 0 0 0 
0 0 0 0

only the first cell of the first column is generating nonzero data. For the third test:

513 514 515 516 
513 514 515 516 
513 514 515 516 
513 514 515 516

all cells in col 1 are generating 513, in col 2 generating 514 an so on.

Now I have to apply these three tests serially to my design, i.e., each column gives out 120 bits (e.g. for col 1 from '1' at the top cell to the 513 at the lowest cell).

I wrote some working Verilog code but have problem in making those 120-bits arrays (due to the part select problem for the col1-3 data arrays):

`define NULL 0

module new_tb;

reg clk;
reg [9:0] cell_sout [3:0];


reg col1_data [119:0]; // Array's col 1 serial data generated by 4 cells
reg col2_data [119:0]; // 3 rounds of testing each time 40 bits generated
reg col3_data [119:0]; // so 40*3 = 120 bits in total
reg col4_data [119:0];

integer file;
integer line;

initial begin

  clk <= 0;

  file = $fopen("array_out_data.dat", "r");
  if (file == `NULL) begin
    $display("there is no file! ");
    $finish;
  end


end

always #12.5 clk <= (clk === 1'b0);

integer i;

always@(posedge clk) begin
// initial begin

  for(i=0;i<12; i=i+1) begin
    
    line = $fscanf(file,"( %d, %d, %d, %d)\n", cell_sout[0], cell_sout[1], cell_sout[2] , cell_sout[3]);
    #10;
    
    $display("cell_sout[0]: %b, cell_sout[1]: %b, cell_sout[2]: %b, cell_sout[3]: %b", 
              cell_sout[0],     cell_sout[1],     cell_sout[2],     cell_sout[3]);
     col1_data[(i*10)+9:i*10] = cell_sout[0];
     col2_data[(i*10)+9:i*10] = cell_sout[1];
     col3_data[(i*10)+9:i*10] = cell_sout[2];
     col4_data[(i*10)+9:i*10] = cell_sout[4];

  end
end

endmodule

How can I achieve this?

Answer 1

To fix the part-select error, change:

 col1_data[(i*10)+9:i*10] = cell_sout[0];

to:

 col1_data[(i*10)+9 +: 10] = cell_sout[0];

Refer to What is +: and -:?

However, you have another problem due to how you declared col1_data. That is an unpacked array, whereas cell_sout is a packed array, and you can't assign them to each other like you are doing. You could make them be the same type. Change:

reg col1_data [119:0];

to:

reg [119:0] col1_data;