# TINA-TI simulation issue with LDO

I'm trying to simulate a circuit, and an LDO is a part of what I'm trying to design.

Input voltage 24 V, output 3V3.

I got a mysterious current on the input of LDO and I can't explain it. Does someone have an explanation?

• R4 is going to destabilize the regulator. Remove it. Also, do you have a capacitor connected to the output? It needs at least 4.7µF at the output to function properly. Commented Nov 9, 2022 at 14:24
• That's rather odd... Could you check the currents on every single pin of the IC? Commented Nov 9, 2022 at 14:35
• I uploaded some picture. added capacitor on the input and output. current on input 20,13mA and others pins(en,fb,gnd,pwpd) negligible Commented Nov 9, 2022 at 14:40
• Why don't you use symbols for VCC, that schematic is hard to read, it would be better if you could put all in one sheet clean it up make it look good and tell us where you're making your measurements Commented Nov 9, 2022 at 14:49
• @VoltageSpike i updated the circuit. sadly in tina ti the zoom doesn't work good Commented Nov 9, 2022 at 15:15

I don't know how you did it, the simulation is good, but the output voltage is not 3.3 V, but 6.1 V. For an output voltage of 3.3 V, one of the resistors must be replaced.

• Thank you for taking time to simulate it. take a look on the ground of the LDO. it's connected to the GND of the supply via a resistor and schottky diode (Loop_gnd to gnd) I did that refer to design reference of 4-20 mA loop current on wich they connect an LDO to power some electronic with ~3,6mA Commented Nov 14, 2022 at 13:41
• If I could see the complete circuit, I would be happy to review it all. Commented Nov 22, 2022 at 6:06

It's because you must have some very large ripple to get it current like that through the cap either that or if you're doing a transient simulation you're not looking at the steady state conditions. Check the voltage and reduce the ripple before the regulator