# Discerning slew rate and bandwidth limitations

What I get is that, considering a 2 stage OTA, we have 2 effects that limit the amplitude and frequency of the amplified signal:

• Bandwidth of the amplifier: as the frequency of the input signal gets higher exceeding the bandwidth, the gain at which it is amplified gets lower
• Slew rate of the amplifier: when an input signal has a higher voltage slope than what the amp is able to provide, the output is pinned to the maximum rate of change

I get that both are caused by the dominant capacitor not charging/discharging fast enough, so how are they different in their effect?

Slew rate limiting occurs when the input signal amplitude (the difference voltage between the inputs) gets large enough to result in all the input stage tail current being sunk alternately down one side of the input differential pair and then down the other over 1 complete cycle of the input signal.

When this occurs the current being pushed and pulled between the first stage and the second stage's compensation capacitor reaches a limiting maximum and so the compensation capacitor charges and discharges in a linear manner.

If the input sine-wave signal amplitude is small enough to ensure that there is spare input stage tail current then the capacitor will charge and discharge in a manner approximating a sine-wave.

The above assumes the usual design situation where the input stage tail current current source is designed to source less current than the second stage current source and therefore the input stage tail current is the limiting factor and in this situation slew-rate could be improved by increasing the input stage tail current.

In the unusual design situation where the second stage current source is supplying less current than the input stage tail current source, then the second stage current source would be the limiting factor for the maximum rate of charge of the compensation capacitor.

The above description is a fairly basic view of the causes of slew rate limitation and in a real amplifier other factors can come into play causing effects such as unequal positive going and negative going slew rates..

• It's misleading to talk about this in terms of cyclic or periodic signals -- slew rate is very much a concern for a step change as well. Although perhaps OP started that by talking about frequency of the input signal. Besides, slew rate limiting definitely can be a problem even if it isn't affecting both slew up and slew down.... for example a sawtooth wave. Commented Nov 10, 2022 at 22:37
• @BenVoigt Sorry if you were mislead.
– user173271
Commented Nov 11, 2022 at 9:24
• This was very helpful, my doubts were sparked by the different way the 2 limitations affect the shape of the signal, this clears it up, thank you Commented Nov 14, 2022 at 10:28

so how are they different in their effect?

• The bandwidth of the amplifier affects small signals as well as large signals
• The slew rate limit affects large amplitude output signals and may not affect smaller amplitudes

Basically, what you implied (to me) in your question.

Using the example of an op-amp, the transistor that is responsible for BW limiting has only so-much current it can use in its collector. This limit of current dictates the maximum dv/dt across the miller feedback capacitor associated with that transistor. Because $$\i=C\cdot\frac{dv}{dt}\$$ and, because $$\i\$$ is limited and $$\C\$$ is constant, dv/dt has to be limited hence, slew rate limiting occurs.

• Thank you for your try, I didn't explain myself well. What is the mechanism by which, increasing the frequency, a large signal gets limited by slew rate and a small signal by bandwidth? I'm not sure what actually happens in the circuit differently in the 2 cases, and why Commented Nov 10, 2022 at 18:58
• Using the example of an op-amp, the transistor that is responsible for BW limiting has only so-much current it can use in its collector. This limit of current dictates the maximum dv/dt across the miller feedback capacitor associated with that transistor. Because $i = C\cdot \dfrac{dv}{dt}$ and, because $i$ is limited and $C$ is constant, dv/dt has to be limited hence, slew rate limiting occurs. Commented Nov 10, 2022 at 19:13
• Okay so, if that transistor is able to provide enough current as we increase the signal frequency, then the output will be limited by the BW at some point; while if the transistor isn't able to provide enough current, then slew rate limiting occurs. Correct? Thank you Andy Commented Nov 10, 2022 at 19:20
• @concernedmiddleageman correct. Commented Nov 10, 2022 at 19:34