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As the title says, I would like to interface an SJA1000 CAN controller to a Xilinx Spartan6 FPGA.

The SJA1000 has a shared 8-bit address&data bus with an address latch signal and either separate read and write strobes, or a read/!write signal and an enable strobe. (ie. a total of 10 interface pins.)

The standard EMC interface core for the Spartan6 only seems to support separate address and data buses, as far as I can tell.

I probably could write something manually which implements the interface but before I go reinventing the wheel I wanted to ask about it -- interfacing to this sort of bus seems like it ought to be fairly common after all.

So is there some way to configure one of the standard Xilinx cores to serve as an interface to this device/bus type? Or is there some other simple off-the-shelf solution?

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Turns out it was simple after all -- I was just looking at the wrong IP core. For future reference, the correct core to use for this scenario is the EPC (external peripheral controller), not the EMC (external memory controller).

The EPC core has options to use a multiplexed address/data bus as expected.

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