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What is the best practice to implement wait states on a 65(C)02? Are there any schematics to use as reference?

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As with any device, its manual should be the first stop for any research. In this case maybe the 6502 datasheet, or if you really want to know, the

MCS 6502 Family Hardware Manual of 1976 for example at Archive.ORG

especially

Section 1.4.2.8 RDY -- Ready

on page 37:

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The mentioned diagram 1.13 shows the application of RDY for read and write (emphasis mine).

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Similar description is found for the 65C02 in the datasheet of its original developer Rockwell:

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As well as in the 2016 65C02S datasheet by WDC:

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Bottom line: No matter what version, whenever you want the CPU to wait for one or more cycles, pull RDY until that need to wait is resolved. The CPU will repeat that cycle as long as it is pulled and continues with whatever is presented during the last.


Any way to solve this for your setup depends on that setup, its structure and needs - including defining why a modern device would need wait states at all.

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    \$\begingroup\$ For applications that wouldn't require more than 10us worth of wait states, I wonder what advantages there are to using /RDY for reads and and having to deal with writes separately, e.g. generating the 6502's clock using the second output of a CD4017 or equivalent which is clocked at twice the desired clock rate, but reset when its count value reaches a value based that's upon the address? \$\endgroup\$
    – supercat
    Commented Oct 31, 2022 at 19:37
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    \$\begingroup\$ It's been a while for me but read and understand the RDY line timing thoroughly. As I recall if you violate some of the timing on the line you can hang the CPU requiring a RESET to recover. \$\endgroup\$
    – jwh20
    Commented Nov 1, 2022 at 16:56

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