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I am a newbie to FPGA development. Any help will be highly appreciated and please forgive me in advance if the question is too obvious.

The board is Chipwhisperer 305 artix-7 fpga. Used tool vivado 2021.1. The ila and vio IP from IP catalogue is used.

  1. Recently, I have been working on a project where the top module has two separate clk as input and where two separate module works for the two different clock domains.Let's say top(clk1,clk2) while clk1->module1, clk2->module2. I have come to know that ila and vio only work in one single clock domain. So, to view the output I have used two ila and two vio. However, they are not working while opened by the hardware manager. Is there any way to view the two different clock domain signals in the ila using vio? If so, what should be the thought process?
  2. Another question, what is the debug_hub, generated by the optimization? Is it correspond to JTAG? Why it only takes one clk while get optimzed? Feel free to let me know if you need any more information or if the question sounds incomplete or needs examples.

Thanks a lot for your valuable time. I have attached my set of codes for using single core ila and vio and then using two ila and two vios.

Single core ila and vio based approach code which didn't work due to having multiple clk domain signals in both ila and vio is attached here:

import common_pkg::*;

module top#(
parameter int NUM_SENSOR=16,
parameter int WIDTH=32,
parameter int NEW_WIDTH=36) (
    input logic clk1,
  //  input logic clk2
  //  en,
  //  rst,
  //  debug,
  //  freq
);

//IO
//input   logic   clk1,clk2;
//clk1 = clk for sensor (fast clock), vio and ila = 50MHz 
//clk2 = clk for all the other modules(slow clock=fast clock/#of cycles)=500KHz



wire    en;
//wire             rst;
wire [15:0]    debug;
wire [WIDTH-1:0] freq[NUM_SENSOR-1:0];
wire [NEW_WIDTH-1:0] count;
wire valid_out;
wire valid_in;
wire rst_process;
wire rst_pipe;
wire rst_aes;
wire Dvld;
wire [NUM_SENSOR-1:0]overflow;

// Modules for clk2
    
top_risc processor(
    .clk(clk2),
    .rst(rst_process),
    .debug(debug));

AES_top aes (
    .clk(clk2),
    .rst_n(rst_aes),
    .Dvld(Dvld)
    );


// Modules for clk1

sensor_adder final_sensor(
    .en(en),
    .clk(clk1),
    .rst(rst_pipe),
    //.valid_in(valid_in),
    .count(count),
    .valid_out(valid_out),
    .overflow(overflow)
    );
    
//ila and vio related to clk1





//if no comment beside signals, it is from clk1 domain 
ila_1 debug_core_ila1(
        .clk(clk1),
        .probe0(count),
        .probe1(valid_out),
        .probe2(overflow),
        .probe3(debug), //output from clk2 domain
        .probe4(Dvld)   //output from clk2 domain
        );
vio_1 vio1 (
  .clk(clk1),                // input wire clk1=50MHz LCM
  .probe_in0(count),    
  .probe_in1(valid_out), 
  .probe_in2(oveflow),   
  .probe_in3(debug), //clk2 domain
  .probe_in4(Dvld),  //clk2 domain
  .probe_out0(en),  
  .probe_out1(rst_pipe),  // clk1 domain
  .probe_out2(rst_process),//clk2 domain
  .probe_out3(rst_aes)    //clk2 domain
  
);

//ila and vio related to clk2

// ila_2 debug_core_ila2(
        // .clk(clk2),
        // .probe0(debug),
        // .probe1(Dvld)
        // );

// vio_2 vio2 (
  // .clk(clk2),                // input wire clk
  // .probe_in0(debug),    // input wire [15 : 0] probe_in1
  // .probe_in1(Dvld),    // input wire [0 : 0] probe_in2
  // .probe_out0(rst_process),  // output wire [0 : 0] probe_out1
  // .probe_out1(rst_aes)  // output wire [0 : 0] probe_out3
// );
    


endmodule

The code with two ila and two vio according to clk domain is given here. It is not working as changing the vio values does not trigger the hardware module and does not generate any outputs to the corresponding modules.

import common_pkg::*;

module top#(
parameter int NUM_SENSOR=16,
parameter int WIDTH=32,
parameter int NEW_WIDTH=36) (
    input logic clk1,
    input logic clk2
  //  en,
  //  rst,
  //  debug,
  //  freq
);

//IO
//input   logic   clk1,clk2;
//clk1 = clk for sensor (fast clock), vio and ila 
//clk2 = clk for all the other modules(slow clock=fast clock/#of cycles)



wire    en;
//wire             rst;
wire [15:0]    debug;
wire [WIDTH-1:0] freq[NUM_SENSOR-1:0];
wire [NEW_WIDTH-1:0] count;
wire valid_out;
wire valid_in;
wire rst_process;
wire rst_pipe;
wire rst_aes;
wire Dvld;
wire [NUM_SENSOR-1:0]overflow;

// Modules for clk2
    
top_risc processor(
    .clk(clk2),
    .rst(rst_process),
    .debug(debug));

AES_top aes (
    .clk(clk2),
    .rst_n(rst_aes),
    .Dvld(Dvld)
    );


// Modules for clk1

sensor_adder final_sensor(
    .en(en),
    .clk(clk1),
    .rst(rst_pipe),
    //.valid_in(valid_in),
    .count(count),
    .valid_out(valid_out),
    .overflow(overflow)
    );
    
//ila and vio related to clk1

ila_1 debug_core_ila1(
        .clk(clk1),
        .probe0(count),
        .probe1(valid_out),
        .probe2(overflow)
        );
vio_1 vio1 (
  .clk(clk1),                // input wire clk
  .probe_in0(count),    // input wire [35 : 0] probe_in0
  .probe_in1(valid_out), // input wire [0 : 0] probe_in3
  .probe_in2(oveflow),   // input wire [15 : 0] probe_in4
  .probe_out0(en),  // output wire [0 : 0] probe_out0
  .probe_out1(rst_pipe)  // output wire [0 : 0] probe_out2
  
);

//ila and vio related to clk2

ila_2 debug_core_ila2(
        .clk(clk2),
        .probe0(debug),
        .probe1(Dvld)
        );

vio_2 vio2 (
  .clk(clk2),                // input wire clk
  .probe_in0(debug),    // input wire [15 : 0] probe_in1
  .probe_in1(Dvld),    // input wire [0 : 0] probe_in2
  .probe_out0(rst_process),  // output wire [0 : 0] probe_out1
  .probe_out1(rst_aes)  // output wire [0 : 0] probe_out3
);
    


endmodule
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  • \$\begingroup\$ And your software platform and device is? \$\endgroup\$
    – Voltage Spike
    Nov 15, 2022 at 6:02
  • \$\begingroup\$ Vivado and artix7 device. \$\endgroup\$
    – Tan007
    Nov 15, 2022 at 6:03
  • \$\begingroup\$ Please edit your question, if there are any other specifics include those also \$\endgroup\$
    – Voltage Spike
    Nov 15, 2022 at 6:05
  • \$\begingroup\$ In what way are they "not working"? It sounds like you're not understanding something in the UI. Note that the multiple ILAs are completely independent -- you need to set up the triggers and arm them individually. I have successfully done this on my own multi-domain projects. The biggest problem I have is time-correlating information among the ILAs. \$\endgroup\$
    – Dave Tweed
    Nov 15, 2022 at 12:38
  • \$\begingroup\$ Hi @VoltageSpike, Thanks a lot for the editing suggestions. I have updated the question attached with the code. Hope it helps to get the idea of what I am trying to say. Will be happy to update the question if needed any further information. \$\endgroup\$
    – Tan007
    Nov 15, 2022 at 17:33

1 Answer 1

1
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I have fixed the issue. So, the issue was related to PLL clock generations. By default, there is only one clock(PLL0) that is set up in the CW305 board. All you have to do is to set up another PLL(PLL1) via the python script. This solves the issue for now. However, using the xdc constraint the clk2 couldn't be generated and was not showing. I believe this is just native to CW 305 board design . I will assume the SAM3U microcontroller can only be used to set up the PLL0 and PLL1.

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