I want to improve an LVDS signal's rise and fall time. With a Cyclone III FPGA, the LVDS signal has a 500 ps rise and fall time.

If I apply these signals to a counter/divider IC like the SY100EP33VKG which has a 100 ps rise and fall time at the output, will the resulting signals rise time change and become 100 ps after the counter, or will it follow the input signals rise and fall time as 500 ps? Could I see any improvement with this arrangement?


1 Answer 1


Yes, you should expect to see a 100 ps rise fall time at the output. The path from the clock to the counter output has a large gain and a circuit which clips the amplitude thus decreasing the rise/fall time.

But if you are concerned about jitter, the damage is done in your 500 ps signal. The time jitter is proportional to the rise/fall time.


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