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I'm working on a power circuit for a device that is usually battery powered.

Most of the time, the device is sleeping and sipping at power around ~5uA, which is great for battery life. In this state, the device will be powered by an LDO with a super low quiescent.

Sometimes, the current is going to get up to 600mA. When this happens, I want to switch the power supply over to a buck converter that's pretty efficient. Most of the time this won't even receive high-side power (blocked via back-to-back P-channel mosfets) to avoid quiescent, because it's not great.

I'm trying to use JLCSMD's SMD parts library, which limits my options (though they have a number of more common parts). I've designed a circuit that just needs a HIGH signal to handle FET switching that will activate/deactivate all the appropriate power paths.

I'm struggling with the current sensing. I want the switchover current to be around 10mA, as beneath that the buck converter I've selected gets pretty badly inefficient. If I want a maximum voltage drop of ~0.2v at full load current (700mA to be safe), I have a current-sensing resistor of 0.2-0.3 ohms. Assuming best-case of 0.3, at 10mA current - which I want to be my switchover - I have 3mV difference to measure.

I'd need a gain of 1MV/V to get this into the range to activate FET gates - and I think I also ought to put a schmidtt trigger or something on here so it happens all at once, rather than gradually.

Is there a way something like this is typically accomplished - or at least a good way to do it?

I was thinking of using a P-channel MOSFET as a voltage-controlled resistor to change the sense resistor value, but that could get hairy. I was also thinking I could may just chain sequential op-amps to amplify repeatedly, but I worry about quiescent inefficiency as well as thermal drift.

Thanks!

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  • \$\begingroup\$ Is there a part of the powered circuit that activates when the current ramps up? A heater? Motor? Lights? It might be easier to pick off the activation signal rather than measure the current draw. \$\endgroup\$
    – vir
    Nov 15, 2022 at 23:44
  • \$\begingroup\$ I've thought about something along those lines, but it's a collection of a few different systems, and the combination of (n) of them is what contributes to the draw... \$\endgroup\$
    – Helpful
    Nov 15, 2022 at 23:51
  • \$\begingroup\$ Can you not current-sense on the unregulated side? Doing so should allow you to use a larger-value current-sense resistor, with more voltage headroom. \$\endgroup\$
    – glen_geek
    Nov 16, 2022 at 0:25
  • \$\begingroup\$ @glen_geekAnother good thought! I should have mentioned in the body: my device is 3.3v and I have a lipo battery, so it gets down to ~3.5v of useful power, which already doesn't leave much room for the LDO/Buck, so... \$\endgroup\$
    – Helpful
    Nov 16, 2022 at 0:39
  • \$\begingroup\$ The buck converter has a startup time. Will it be fast enough? \$\endgroup\$
    – Jens
    Nov 16, 2022 at 1:51

1 Answer 1

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This is the approach I would use to start an evaluation:

schematic

simulate this circuit – Schematic created using CircuitLab

  • The linear regulator will start first and charge the large buffer capacitor C2, that is needed for the takeover period.
  • The output of OA1 will initially be low because the voltage at IN+ is around 1.5mV below the voltage at IN-. This is close to the offset error and R3 may need an adjustment.
  • R1 is the shunt for current measurement. A rising load current introduces a falling voltage at IN- and if this falls below the voltage at IN+ the output voltage of OA1 rises close to 3.3V. The 220 mΩ is just a guess.
  • The positive feedback of R4 modifies the reference voltage at IN+ a little bit to avoid unstable states (hysteresis).
  • The buck converter starts after the rising edge of the OpAmp output. The regulation setpoint of the buck converter should be 0.1V above the LDO output to disable the LDO current path.

There are still problems to consider:

  • The buck converter must be able to start into a precharged output, some can, others can't.
  • The current through R6 and R5 may ruin the quiescent current consumption. A decoupling diode is not an option here, because there is not enough voltage margin from the battery.
  • Some buck converters force the output voltage down if disabled. This would be a no go here.
  • Undervoltage lock out is not properly solved. The battery may run into deep discharge.
  • The switchover current level is not well defined because the offset error of OA1 plays a significant role here. It is hard to find amplifiers or comparators with very low supply current and low offset errors.
  • The value of R4 may be too low, increase the value for less hysteresis.
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  • \$\begingroup\$ Assuming choosing the LPV521 is important - what parameters are driving this decision? What calculations will help me understand what variation in R3 may be necessary? I'll put back-to-back PMOS between the supply and the buck, so the opamp can connect those and the quiescent of the buck shouldn't matter much even with R5/6. -I'll also put a high-side switch/ideal diode between it and the 3.3v line to avoid output voltage discharge on disable. How undefined is the switchover current? Link to the math for this opamp arrangement so I can dig in would be really appreciated. \$\endgroup\$
    – Helpful
    Nov 16, 2022 at 4:41
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    \$\begingroup\$ I filtered OpAmps by supply current below 1 uA, offset error below 0.5 mV, output slew rate above 2 V / ms, rail to rail input voltage range, affordable price and market availability. There were only very few and this one was best match in offset error. (R2 parallel to R4) / R3 form a voltage divider and define the minimum voltage at the shunt for takeover. The voltage across R3 will be compared with the shunt voltage. This would be 1.5mV for an ideal OpAmp. The offset error, typically 0.1 mV, changes this trigger level in a random direction. You may end up with 3.9 kohm for R3. \$\endgroup\$
    – Jens
    Nov 16, 2022 at 5:04
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    \$\begingroup\$ You must invert the OpAmp output with a CMOS gate or NFET to enable the PMOS switches, they a conducting with gate close to GND. \$\endgroup\$
    – Jens
    Nov 16, 2022 at 5:04
  • \$\begingroup\$ I was planning on using an NFET for PMOS gate switch. I'll look over all these numbers and see what I can work out! Thank you 1000x, this really helps. I was worried that the requirements might be too extreme. For the record, I think my battery could tolerate another 5uA of quiescent, just trying to avoid it getting out of hand - so I may broaden those search requirements some. \$\endgroup\$
    – Helpful
    Nov 16, 2022 at 5:09
  • \$\begingroup\$ I'm gunna leave the question open a little longer, but I anticipate I'll be selecting yours for the answer, barring somebody suggesting something that solves the problem in a much more direct way. \$\endgroup\$
    – Helpful
    Nov 16, 2022 at 5:11

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