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I am reading about structural hazards in pipelined architecture in processors. In classic RISC pipeline one such hazard is when we write and read simultaneously to same register, which may cause hazard on real Silicon (Write back stage section in Wikipedia article).

While searching for solutions to solve this hazard, there is this statement I found about register files to mitigate the hazard -

enter image description here

I have read similar statement in multiple sources. But it's not clear how this can be implemented in digital logic like RTL. Typically, writes and reads both are implemented in rising edge of clock if we implement register file in RTL. So how can we implement write in "first half" and read in "second half" of clock cycle?

source of screenshot

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    \$\begingroup\$ That's an implementation detail that's normally hidden below the level of abstraction we call "RTL". It depends on whether your register file is constructed using edge-triggered devices or level-sensitive latches. In the former case, you'd update them on the falling edge of the clock (assuming that everything else happens on the rising edge). In the latter case, you'd literally enable the latch during the first half of the clock. \$\endgroup\$
    – Dave Tweed
    Nov 17, 2022 at 21:40
  • \$\begingroup\$ It is possible to build a flipflop that writes on the rising edge and reads on the falling edge or vice versa. \$\endgroup\$
    – user253751
    Jan 16, 2023 at 17:53
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    \$\begingroup\$ Ok... but I don't want to mix posedge and negedge in RTL as it adds complexity to timing analysis and synchronisation of pipeline. \$\endgroup\$ Jan 17, 2023 at 20:49

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To mitigate structural hazard in Register File, use separate read and write ports as the book says.

Now comes the problem of data collision...

how can we implement write in "first half" and read in "second half" of clock cycle?

As Dave hinted, this is something you don't have to worry about in RTL. It is actually hidden from RTL abstraction and rather implemented in the memory cells itself to avoid data collision due to simultaneous read and write to same address.

Suppose you want to implement Register File in Block RAM (True dual port) on FPGAs. In such cases you may want to ensure a timing delay between the read and write clock edges to avoid data collision. This timing requirement is usually given in the RAM datasheet itself.

As an example: I found a document from microsemi which you may find useful. It talks only about data collision (read-read, write-read, read-write, write-write) on dual port SRAMs on FPGAs, and how to time the read and write clock edges to avoid getting an unknown or 'X' value.

Data collision is inherent to memory cells like SRAM. Instead of RAM cells, you can simply implement Register File using flip-flops and muxes/decoders in RTL. You will find this implementation in most of the opensource RISC cores out there. Something like this:

enter image description here

Now, you don't have to worry about the problem of data collision as you can always read and write to a flip-flop on same clock edge. You will always read the 'older' value, provided that setup and hold timings are met.

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