Suppose you have a 64-byte cache on a system with 16-bit memory addresses. If the cache is direct-mapped and it has 10 bytes of tag overhead in total, how many bits are used for the tag, index, and block offset within the 16-bit memory address?
I found this in the textbook Computer Organization and Design by Patterson and Hennessy, and I was hoping someone could work through it for me. In particular, I'm curious as to what "10 bytes of tag overhead" is and how it effects what the solution is. How are the tag, index, and block offset generally found given some cache design?