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I have created a 4th-order filter based on the result of calculations and simulation. Bellow is schematic:

enter image description here

In simulation the filter works fine (I also checked the transfer function using this online tool) but in the real world, it doesn't.

I use a 5 V phone charger as a power supply. On the output of the filter there are voltage oscilations (yellow plot). The blue plot is the output of a differential amplifier, and it looks fine. I found that there are small oscillations after resistor R8, so on the input of the filters.

enter image description here

enter image description here

The filter has negative poles negative so it is stable. Also on the filter input I pass a constant 5 V signal. As depicted in the schematic I use a second sine voltage source to check attenuation of the filter, but in the real world I just pass a constant signal.

What is the cause of these oscillations?

Edit:

Calculations:

enter image description here enter image description here enter image description here enter image description here enter image description here enter image description here enter image description here

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  • \$\begingroup\$ Comments are not for extended discussion; this conversation has been moved to chat. \$\endgroup\$
    – Voltage Spike
    Commented Nov 19, 2022 at 2:05

3 Answers 3

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Intro

Thanks for showing what you are doing. At least I know you are following some process.

I'm going to ignore it. I don't have the textbook (not even its name) handy, so I'm not prepared to compare its approach to what follows. I'll leave that to you.

All I can do is follow an approach I imagine I know.

Sallen-Key

I can see that you are using one of the standard 2nd order Sallen-Key low-pass filter topologies. So that gives me a starting point as I actually do have their paper and have read it more than a few times. (I'm slower than some, so it takes me time to let things sink in.)

Let's look at this 2nd order Sallen-Key low-pass filter topology:

schematic

simulate this circuit – Schematic created using CircuitLab

If we assume that \$R_1=R_2=R\$ and \$C_1=C_2=C\$ (equal value components for those) then we find that \$\omega_{_0}=\frac1{R\,C}\$, which is expected.

But more curiously that \$2\zeta=2-\frac{R_4}{R_3}\$. We also know that the gain is \$k_i=1+\frac{R_4}{R_3}\$. So it appears that the ratio \$\frac{R_4}{R_3}\$ simultaneously impacts both the damping \$\zeta\$ (or \$Q\$) and the gain.

We can't specify that ratio, independently.

Butterworth

The 4th order Butterworth does solve out as having two characteristic equations:

$$s^2 + 1.84775906502257\cdot s + 1.0\\\\s^2 + 0.765366864730179\cdot s + 1.0$$

(These are in analytic form where \$\omega_{_0}=1\$.)

The middle constants you see there represent \$2\zeta\$. So in the first case we know that the ratio \$\frac{R_4}{R_3}\approx 0.152241\$ and in the second case that the ratio \$\frac{R_4}{R_3}\approx 1.234633\$.

This also means that the gain in the first case will be \$k_1\approx 1.152241\$ and in the second case will be \$k_2\approx 2.23463314\$. The combined gain is then \$k_1\cdot k_2\approx 2.57484\$ (or \$+8.215\:\text{dB}\$.)

There's nothing much really to be done about that. The gain comes along for the ride. With this topology you don't get to pick and choose.

These relationships are pretty much set in stone by the definition of a Butterworth. We could make adjustments. But that would mean changing the middle factor in each characteristic equation and the product of the two would no longer match the 4th order Butterworth form.

Design

I don't want to try and design your work product. I don't know enough yet. But it's also not important. The above sets the stage and you should be able to go from there.

So, I just happen to want to set the capacitors, first. (They have fewer choices per decade than resistors, anyway.) Let's set \$C=33\:\text{nF}\$. Now, I have decided to also like \$f_{_0}=400\:\text{Hz}\$. From this, I find that \$R= 12\:\text{k}\Omega\$ gets close. As a result \$f_{_0}=401.9\:\text{Hz}\$. Close enough.

Now, there's an issue about that ratio \$\frac{R_4}{R_3}\$. How do I pick values? We could dig into input bias currents and the impedance seen by both opamp inputs. That's for another day. For now, I feel a solution towards getting an \$R_4\$ value of about half of \$12\:\text{k}\Omega\$ for the 1st stage is good enough and it says that I will need \$R_3\approx 39\:\text{k}\Omega\$.

With \$\frac{R_4}{R_3\,=\, 39\:\text{k}\Omega}\approx 0.152241\$ find \$R_4=5.937\:\text{k}\Omega\$. I'm going to keep that number of places for the simulation. So that's settled.

For the 2nd stage it is \$\frac{R_4}{R_3\,=\, 39\:\text{k}\Omega}\approx 1.234633\$. Find \$R_4=48.15\:\text{k}\Omega\$. Now that's also settled.

The final schematic is:

schematic

simulate this circuit

Simulation

Okay. Now a simulation might be in order.

(Remember what to expect for the cutoff: it's \$\omega_{_0}=\frac1{12\:\text{k}\Omega\,\cdot\,33\:\text{nF}}\$ or \$f_{_0}\approx 401.91\:\text{Hz}\$.)

I like the LT1800 for simulation. Nice rail to rail I/O (and too expensive for my blood.)

Let's see:

enter image description here

Okay. Not bad. We are looking (in the Butterworth case it's correct to do so) for the \$-3.01\:\text{dB}\$ point to get a bead on \$f_{_0}\$. (This is also the inflection point for the phase.) And there it is in the blue oval. Just where we figured it would be. (Note the top green oval wraps a value of about \$+8.21\:\text{dB}\$ and that if we add \$-3.01\:\text{dB}\$ to that we get \$+5.20\:\text{dB}\$, which shows in the lower green oval.)

Also, take note that above \$+8.215\:\text{dB}\$ was predicted for the Butterworth. The top green oval circles that value (of course.)

Summary

Not much more to add to the design bits.

In simulation I'm using bipolar supplies and the signal is ground-centered. In your case, what I see is a unipolar supply rail for the opamps. I'll assume you already know about adding DC bias to the input signal.

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Based on the schematic, it looks like you've incorrectly wired the Sallen-Key configuration. We should have the output fed-back to the inverting input through resistors R11 + R18 (U1) and R13 + R15 (U2), then R10/R14 complete the voltage divider. Instead we have Vo connected to the inner node of the voltage divider:

enter image description here

I quickly tried to derive the transfer function assuming infinite input impedance on the amplifiers, and with this assumption current can't flow from Vo to V- meaning Vo = V- = V+. I found that this results in a situation were there is more than one solution. Using the Sallen-Key component numbering and calling the inner node between R1 and R2 Vx, KCL at the non-inverting input is

$$\frac{V_x-V_{out}}{R_2} = C_2sV_{out}$$

and at the output

$$C_1s(V_x-V_{out})=\frac{V_{out}}{R_3}$$

Thus we end up with two function of Vx as a function of Vout, which as far as I can tell can't both be simultaneously satisfied except for a trivial solution where all voltages are 0. This suggests to me that you are seeing some very non-ideal system characteristics which could be giving you those oscillations.

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After some re-wiring filters ...

Here is what you should get.

enter image description here

enter image description here

Behavior of filters.

enter image description here

One can add some offset (wire R13 to R4 & R1) and modify RG (I used 500k) for more gain ...

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