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After synthesizing my RTL level design into verilog netlist, I find the syntax confusing. Here is what I mean.

RTL compiler gives me:

  MUX2X1 g11005(.A (n_741), .B (\in_a[9] ), .S (n_2197), .Y (n_1063));

What is "\in_a[9]"?

XST gives me:

  wire [1 : 0] \inv/qmul/p ;

What is "\inv/qmul/p"?

Are "\" and "/" even eligible in verilog naming conventions?

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The verilog escaping mechanism is to put \ at the start of an identifier and a " " at the end. The trailing space is mandatory. Within those, anything is a legal verilog name. It's pretty ugly.

It looks like the compiler has "flattened" part of the design, what might have been inv.qmul.p has become one identifier and the module hierarchy has gone.

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The \ is an escape character, which escapes the entire string of ascii characters until the next space character (note the space before the closing parenthesis of .B).

So \in_a[9], is literally just a net named in_a[9]. It's no longer part of any bus, it's just a net name that happens to have some brackets in it. Similar for inv/qmul/p, this is just a net name with some slashes in it (I've seen synthesizers generate nets like this when it wants to preserve a net's original hierarchy for some reason, though I couldn't say exactly why).

I think that you could have a verilog net named wire \@#$%{{[[@#$^@ ; and it wouldn't complain, but of course I've never tried :)

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  • \$\begingroup\$ Thank you for the explanation. I am not sure if \in_a[9] is a net named in_a[9], because I stimulate a design in modelsim, and it tells me that I have a signal called "\in_a[9]". It looks like that is the name of the signal. \$\endgroup\$ – drdot Apr 3 '13 at 22:57
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See the clunky Verilog Formal Syntax Specification for <IDENTIFIER>

An identifier is any sequence of letters, digits, dollar signs ($), and underscore (_) symbol, except that the first must be a letter or the underscore; the first character may not be a digit or $. Upper and lower case letters are considered to be different. Identifiers may be up to 1024 characters long. Some Verilog-based tools do not recognize identifier characters beyond the 1024th as a significant part of the identifier. Escaped identifiers start with the backslash character () and may include any printable ASCII character. An escaped identifier ends with white space. The leading backslash character is not considered to be part of the identifier.

Taking your example wire [1 : 0] \inv/qmul/p ;. The wire is named inv/qmul/p, typical of a hierarchical (modular) design being flattened.

Since inv/qmul/p is not a valid 'bare literal' in Verilog (due to the forward slashes) it is written as an escaped identifier. The escape mechanism is to prefix with backslash \ and append whitespace .

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  • \$\begingroup\$ Thank you for the helpful reference and the explanation :) \$\endgroup\$ – drdot Apr 5 '13 at 15:50

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