After synthesizing my RTL level design into verilog netlist, I find the syntax confusing. Here is what I mean.
RTL compiler gives me:
MUX2X1 g11005(.A (n_741), .B (\in_a ), .S (n_2197), .Y (n_1063));
What is "\in_a"?
XST gives me:
wire [1 : 0] \inv/qmul/p ;
What is "\inv/qmul/p"?
Are "\" and "/" even eligible in verilog naming conventions?