How can memories be implemented efficiently with memory blocks of different sizes?

Question

I am unsure if I am framing the question correctly, but here's what I wanted to ask.

Let's say we want to implement a 64 kB memory. We would require a 16-bit address if we have byte-addressable memory.

One simple way would be to use a complete 64 kB block. Another approach would be to use four blocks of 16 kB each and the lower 14 bits of the 16-bit address and feed it into each memory block, and use the higher-order 2 bits to select which memory block this address points to. This implementation is fairly simple.

But what would happen if we had memory blocks of variable sizes? Say, we have four 4 kB memory blocks, two 8 kB memory blocks, and two 16 kB memory blocks.

How would we have an implementation, as I mentioned above? I don't see any practical benefits of this approach. I just wanted to ask if and how this can be implemented.

Answer 1

Since all your memory blocks are powers of 2 in size, implementing it is still straightforward.

Your first example (1 block of 64 KB) requires no address decoding. Your second example (4 blocks of 16 KB) requires some address decoding, as you've mentioned.

Your third example just requires more address decoding.

As you mentioned, you need a 16-bit address for the full 64 KB memory. It is common to represent that as A[15:0], where A[15] is the MSB.

You would directly connect the lower 14 MSB's to the 14-bit address input of each 16 KB block: A[13:0]. For the 8 KB blocks, you would similarly connect the lower 13 MSB's to the 13-bit address: A[12:0]. For the 4 KB blocks, you would connect the lower 12 MSB's to the 12-bit address: A[11:0].

The chip-select input for the 1st 16 KB block would be an address decode of the 2 MSB's. The 1st block is selected when A[15:14]=0. The 2nd block, when A[15:14]=1.

The 2 8 KB blocks are selected when A[15:14]=2: the 1st 8 KB when A[13]=0, and the 2nd 8 KB when A[13]=1.

And so on.