# How can memories be implemented efficiently with memory blocks of different sizes?

I am unsure if I am framing the question correctly, but here's what I wanted to ask.

Let's say we want to implement a 64 kB memory. We would require a 16-bit address if we have byte-addressable memory.

One simple way would be to use a complete 64 kB block. Another approach would be to use four blocks of 16 kB each and the lower 14 bits of the 16-bit address and feed it into each memory block, and use the higher-order 2 bits to select which memory block this address points to. This implementation is fairly simple.

But what would happen if we had memory blocks of variable sizes? Say, we have four 4 kB memory blocks, two 8 kB memory blocks, and two 16 kB memory blocks.

How would we have an implementation, as I mentioned above? I don't see any practical benefits of this approach. I just wanted to ask if and how this can be implemented.

• Two 8192 blocks can be achieved with 14 bits for instance. Maybe I'm not seeing your issue? Commented Nov 20, 2022 at 12:25
• In your first example, just think of a single 16 kB block as two 8 kB subblocks which use an extra bit for selection. Then, one of those 8 kB block is itself subdivided into 2 x 4 kB using the next bit. Commented Nov 20, 2022 at 12:38
• Yes it's just a simple extension of your simple approach.
– user16324
Commented Nov 20, 2022 at 12:50
• Do you mean RAM or Flash memory? But it does not really matter. You can mix and match any size blocks to implement any total size, as long as the address decoding for it works. Commented Nov 20, 2022 at 12:52
• @Nicolas Yeah, I think it was a brain fade moment for me. I wanted to ask about any variable-size block. I example I gave really simplified the problem. Commented Nov 20, 2022 at 13:12

## 1 Answer

Since all your memory blocks are powers of 2 in size, implementing it is still straightforward.

Your first example (1 block of 64 KB) requires no address decoding. Your second example (4 blocks of 16 KB) requires some address decoding, as you've mentioned.

Your third example just requires more address decoding.

As you mentioned, you need a 16-bit address for the full 64 KB memory. It is common to represent that as A[15:0], where A[15] is the MSB.

You would directly connect the lower 14 MSB's to the 14-bit address input of each 16 KB block: A[13:0]. For the 8 KB blocks, you would similarly connect the lower 13 MSB's to the 13-bit address: A[12:0]. For the 4 KB blocks, you would connect the lower 12 MSB's to the 12-bit address: A[11:0].

The chip-select input for the 1st 16 KB block would be an address decode of the 2 MSB's. The 1st block is selected when A[15:14]=0. The 2nd block, when A[15:14]=1.

The 2 8 KB blocks are selected when A[15:14]=2: the 1st 8 KB when A[13]=0, and the 2nd 8 KB when A[13]=1.

And so on.

• Is there any way to implement it if we have memory, not in the power of 2? Commented Nov 20, 2022 at 13:10
• @VedantaMohapatra: In general, yes. Commented Nov 20, 2022 at 13:20
• Can you kindly extend your answer to include that too? Commented Nov 20, 2022 at 14:02
• @VedantaMohapatra In reality you would never try to build (let's say) a 16 KB range out of 5 memory blocks each 3 KB and one of 1KB. You assign a "slot" with a size of a power of 2 to each block, accepting the gap. Why are you asking? Commented Nov 20, 2022 at 17:25
• @thebusybee It was essentially just for theoretical understanding. I thought of the method you said, but as you said, it wastes bits. So, I was asking if there are any other methods. Commented Nov 20, 2022 at 17:28