So I'm going through my textbook and I'm stuck on this problem:
Design a circuit that has two inputs, \$clk\$ and \$X\$, and produces one output \$O\$.
- \$X\$ may change every clock cycle, and the change happens at the falling edge.
- The circuit samples the input at every rising edge of the clock.
- If the input is \$1\$, consider as read a \$1\$, else read a \$0\$. \$O\$ is \$1\$ (for one clock cycle, from positive edge to positive edge) if the last three bits read are \$110\$, with \$0\$ as the most recent bit.
Draw the state diagram. Close to an arc, show \$X=1\$ or \$X=0\$ to indicate whether the change of state happens when \$X=1\$ or when \$X=0\$.
How would one approach this problem?