I'm using a 74HC93 as a counter. According to the datasheet @ 25°C and 6V:

  • propagation delay CP0 to Q2 = 31 ns
  • transition time = 13 ns
  • max. clock frequency = 35 MHz = 28.56 ns

From what I've searched, propagation delay is the time it takes for the signal to move from input to output pins, while the output transition time is the time for the signal to settle at a specified level.

This means the total amount of time for the signal to appear at the output is 31 ns + 13 ns = 44 ns which is higher than the max. clock period (from the max. frequency) of 28.56 ns. Why are they different?

Wouldn't this mean that by the time the output appears at the output pin, which would take 44 ns, the clock would've almost pulsed again at 28.56 ns? So wouldn't this mean that we can't use the max. clock frequency?


2 Answers 2


Prop delay is usually measured between the 50% transition points of the input & output. So if the input (CPO) and the output Q2 both have 13 ns transition times, the prop time would be measured between the 6.5 ns points of the two signals.

Here's a timing diagram from the TI datasheet for the 'HC161 binary counter, SCLS297D. Note how the prop time, Tplh is defined.

enter image description here

The transition (rise/fall time) is not added to the prop time.


An analogy;

Imagine a line of people 1000 people long.

You whisper a word to the first guy. A single word every second, and he repeats to the next guy, a second later. And so on, until the last guy does something with it, say he writes it down in a book.

You are clocking in data at 1hz, but the propagation delay to the end of the line is 1000seconds. To get a sentence like "The quick brown fox jumps over the lazy red dog." across takes 10clocks plus propagation delay, or 1010 seconds.

The first word is written in the book after the propagation delay, but you could clock this circuit of people 999 times before that first word is written.

Now imagine these people are transistors moving bits. Same concept.


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