I'm trying to produce a signal using a 74HC93 that pulses high every 8th bit while the "SELECTOR" signal is low. The "SELECTOR" signal is 24 clock cycles.

It works fine at 4 MHz, but when the frequency is increased to 10 MHz the output is not what is desired, and it pulses at weird times.

My circuit:

enter image description here

The output I'm getting at 10 MHz (blue):

enter image description here

The expected output (blue) is something like:

enter image description here

74HC93 - counter
74HC08 - AND gate
74HC14 - inverter

Input voltage of 3 V
Clock frequency 10 MHz (same circuit works at 4 MHz)

  • 1
    \$\begingroup\$ What is the datasheet of the exact chip you are using? What exactly is your supply voltage? Note the field Maximum clock frequency and Input transition rise/fall time in the datasheet \$\endgroup\$
    – Ferrybig
    Commented Nov 22, 2022 at 9:05
  • \$\begingroup\$ 74hc93 for the counter, 74hc14 for the inverter, and 74hc08 for the AND gate. supply voltage is 3V. i've calculated the max frequency of the 74hc93 at 3v and its around 17Mhz which should be fine for the 10Mhz frequency i'm using \$\endgroup\$
    – red
    Commented Nov 22, 2022 at 9:12
  • 1
    \$\begingroup\$ Please can you edit your question to add any new info, rather than in comments. Otherwise, readers have to piece together the full question from scattered fragments. Can you what and where your CLOCK and SELECTOR sources are. If they're coming up wires, for instance, you'd get more skew and distorted waveforms than across PCB tracks from nearby ICs. At first glance, this problem looks like the propagation delays of the ICs having a bigger effect on a shorter CLOCK and signal periods. \$\endgroup\$
    – TonyM
    Commented Nov 22, 2022 at 11:18
  • 3
    \$\begingroup\$ Your feedback circuit is a chain of 5 gates. The propagation delay through this chain is what's limiting your maximum usable frequency. \$\endgroup\$
    – Dave Tweed
    Commented Nov 22, 2022 at 11:50
  • \$\begingroup\$ If this was every 8th clock cycle: Anything wrong with clocking the by-8 section only, generating the required output from a three-input AND (equivalently NOR if high in first cycle was as good as as in last cycle out of every 8)? \$\endgroup\$
    – greybeard
    Commented Dec 3, 2022 at 13:26

2 Answers 2


As Dave Tweed has pointed out your chain of feedback gates is limiting the maximum frequency.

The solution is to use a 74HC10 three input NAND gate instead of the 74HC08. Inverting gates in CMOS are generally faster than non inverting gates. The non inverting gate internally consists of a inverting gate followed by an inverter.

So substitute a three input NAND for U5B U5C and U6A. Use another 3 input NAND for U5A and U6C, Tie the unused input to VDD. This brings the number of gates in your feedback path down from 5 (effectively 8 because of the hidden inverters in the non inverting gates) to 2.

You can also use the unused 3 input NAND as an inverter (connect inputs together) to substitute for U6B saving a package.


Don't know if this can help you, but you should check the "timing" ...

enter image description here

enter image description here

If you change the polarity of the clock... looking at the "falling" edge ... and pulses output at Q3 ... there are 8 bits.

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  • 1
    \$\begingroup\$ @RoyC You could use a second 3-input NAND for U3 (by tying two of its inputs together, or tying one of them high), and a third for U5 (tying all three inputs together, or tying two of them high). Since you can get 3-input NAND gates in three-gate packages, that seems like a workable solution to me. \$\endgroup\$
    – Hearth
    Commented Nov 22, 2022 at 16:37

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