I'm trying to build a frequency counter with a resolution of 1 Hz that will count any frequency between 0 and 999 Hz and hold that value. I've built the following in Multisim but I'm having trouble getting it to work.

The block diagram is the part inside the red perimeter...

enter image description here

Circuit in Multisim...

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Here the frequency I want to display is the 120Hz signal. However, it only counts rather than directly displaying the 120Hz frequency and I've been able to get it to display up to 112 in Multisim after letting the simulation run for about an hour.

enter image description here

Also there is a bug in Multisim that prevents the crystal from working properly, which is why the digital clock is used to produce the 32.768kHz signal as show here:

enter image description here enter image description here

UPDATE: I was able to get it to count to 234 and then reset to 000 with the following: enter image description here

Can someone please tell me how to get it to hold the final count value?

  • \$\begingroup\$ I guess my first question has to do with the counters. The datasheet specifically says that if the mode is fixed, and in your case it most definitely is fixed, the OR gates are not required. Why add them here? My second question is to ask if this problem is homework. Is it required to use CD4029? Or would you be willing to consider other (possibly better) combination parts? My third question is because I'm not putting time into this yet. How are you locking in a value until the next time you re-count and refresh? \$\endgroup\$
    – jonk
    Nov 23, 2022 at 18:39
  • \$\begingroup\$ Are the counters counting? \$\endgroup\$
    – RussellH
    Nov 23, 2022 at 19:39
  • \$\begingroup\$ I've removed the OR gates but now the display reads 988 instead of 999 as shown above. I'm using the CD4029 because they are the only counters I have. I'm not sure how to lock the value in. I have plenty of cd4027 J-K flip flops and logic gates but I'm unsure of how I could use a modulus counter to do it. \$\endgroup\$
    – Licentia
    Nov 23, 2022 at 21:00
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    \$\begingroup\$ Why don't you just buy an MCU dev board for like 5 bucks, then taking this as an input can be done on a timer, or as an interrupt to the mcu, or you could filter and read it on an adc or... Many options that could be coded in a matter of hours and leave you open to improve/change it as desired later \$\endgroup\$ Nov 30, 2022 at 4:47
  • 1
    \$\begingroup\$ To get the display to hold its value you must use the 4543s' LD pin. You have it tied high so the latching (hold) feature is permanently disabled. You need to bring that line low after the 4029s have reached their final count. Using the falling edge of 0.5Hz to both reset the 4029s (via the inverter) and latch the 4543 (via LD) is a bit of a race condition but would probably work in a real circuit because inverter delay makes latch occur before reset. But maybe your simulator ignores that delay. NANDing 0.5Hz, 1Hz, and NOT 2Hz generates a LD that is safely within stable count window. \$\endgroup\$
    – td127
    Nov 30, 2022 at 22:52

4 Answers 4


You need a way to reset your counter before starting a new count.

The circuit below may suffice:

enter image description here

It uses the 4029 to generate the last bits of the divide down chain to produce the 0.5Hz signal. When 0.5Hz is low it enables the counters via their active low Clock Enable pin. When 0.5Hz goes high the counter stops and holds its value. Near the end of the 0.5Hz cycle the first 4029’s TC asserts. If we invert that we can use it to reset the counter to zero.

The 4543 includes a latch so if we generate a latch signal while the count is stable we’ll get a clean reading. AND’ing 0.5Hz and 1Hz together provide this latch signal.

EDIT I've added an LTspice simulation of the counter section (I don't have a 4543 model). 3.2seconds into the simulation the counter reads 124 as expected. After only 1 second it reads only 124*.9 = 112 because the pulse width of the gating 0.5Hz has an extra 8Hz tick at startup.

Use a NAND gate (for the 4543) if you want to see the count incrementing, or an AND gate if you just want it to latch the final output.

enter image description here

FINAL EDIT Here's an update with my final attempt:

The 4029 counters begin counting when 0.5Hz goes low (enabling their CE pin) and stop counting one second later when 0.5Hz goes low.

The counter outputs will remain stable while 0.5Hz remains high so we generate a LD signal during that time which will allow the counter value to be latched into the 4543s.

LD then deasserts so the 4543 now latch the captured value.

Towards the end of the 0.5Hz cycle the Terminal Count of the 4029 clock generator asserts and we use that to clear the 4029 counters (via the PE pins).

With this circuit the 7-segment displays will only show new values, updating every two seconds.

enter image description here

  • \$\begingroup\$ By building the circuit you've provided I was only able to get it to start counting by keeping the NAND gate and removing the NOT gate from the latch. Since it counts slow in Multisim I decreased the 32.768Khz signal to 500Hz. However, it went past 123 Hz without stopping. Also what's the best way to reset? Should I put a reset switch on the MR pin of the 4060? \$\endgroup\$
    – Licentia
    Nov 25, 2022 at 2:20
  • \$\begingroup\$ With this circuit you won't see the display counting: it only gets updated when the count is finished. If you want to see it counting then just tie the 4543 LD pins low and skip the AND gate. You can't decrease the 32KHz because then the 0.5Hz will be much lower. To debug this, have your simulator display the signals in the above timing diagram. You should see the counter counting while 0.5Hz is low and hold that value when it is high. If it counts past 123 it's because there are more than 123 edges during 0.5Hz high which means the 0.5Hz and/or 123Hz frequencies aren't accurate. \$\endgroup\$
    – td127
    Nov 25, 2022 at 2:56
  • \$\begingroup\$ You don't need to reset the 4060. That's just a free-running oscillator to generate the 0.5Hz signal. Only the three counter 4029s need to be reset between counts. If you want to speed up your simulation just skip the 4060 and put an 8Hz input into the 4029 that generates the 4, 2, 1, and 0.5Hz signals. \$\endgroup\$
    – td127
    Nov 25, 2022 at 3:02
  • \$\begingroup\$ I've added a screenshot of what I have in Multisim but it doesn't count and remains stuck at 000 no matter how long I wait. I've also built it in hardware and the result is the same. @_@ \$\endgroup\$
    – Licentia
    Nov 25, 2022 at 22:29
  • \$\begingroup\$ OK, so it doesn’t work. Why not? Maybe the design is bad (sorry), or maybe you wired it wrong, or maybe a chip is bad, or maybe the power rails are wrong, or a wrong pinout, or.. I could make a guess but it would be much more efficient (and fun) for you to try to debug it. I’d start with the 0.5Hz: is it really there? If you don’t have a ‘scope or voltmeter then wire up an LED to it (with ~5K resistor) – you should see it blink every second. If it’s not there then something’s wrong in the oscillator section. If it is there then problem is after, in the counter maybe. Divide and conquer! \$\endgroup\$
    – td127
    Nov 26, 2022 at 2:34

It sounds like a timing problem with the latch and reset signals. Years ago there was an article in Popular Electronics (Feb. 1980) about CMOS counter ICs that had a simple latch/reset circuit using a CD4011 quad NAND gate.

It's simply two differentiators that take the clock signal and create delayed pulses such that at the end of the counting period it would latch the final value into the display and then reset the counter. I used this in a digital capacitance meter and it worked well, I was even able to add a 555 timer to delay the reset pulse to cancel out any stray readings.

Perhaps this circuit could be adapted to your counter.


simulate this circuit – Schematic created using CircuitLab


Follow the chaining instructions found in the datasheet. the OR pattern looked good.

you will need to drive ~PE somehow from the 2Hz clock

you will probably want to drive LD from that clock also

  • \$\begingroup\$ I've tried tying PE and LD to 2Hz on the Q13 pin of the 4060 but the display starts at 000 and never changes. I've included a screenshot above. \$\endgroup\$
    – Licentia
    Nov 23, 2022 at 23:53
  • \$\begingroup\$ one or both of them probably needs to be inverted and/or delayed \$\endgroup\$ Nov 24, 2022 at 0:02
  • \$\begingroup\$ Putting an inverter between Q13 of the 4060 and PE of U4 and an inverter between Q13 and LD of U11 causes the display to read 011 from left to right. \$\endgroup\$
    – Licentia
    Nov 24, 2022 at 4:09
  • \$\begingroup\$ you may have to run a time domain simulation for figure out how it gets that result. \$\endgroup\$ Nov 24, 2022 at 4:20

Consider the MC14553B. This is a three-digit up-counter complete with an onboard latch and a multiplexed output for the displays. This could replace many of the individual ICs in your design.


Also, it is not clear how you want the circuit controlled. Is it supposed to count and display the input frequency just once, and freeze the display (waiting for some kind of reset)? Or count, latch the display, zero the counter, count the input, and update the display - continuously?

  • \$\begingroup\$ I don't have a MC14553B. I have a bunch of J-K flip flops, CD4029's and logic gates. I want the display to update every second and hold the value of the input frequency. I'm not sure how to do that yet. \$\endgroup\$
    – Licentia
    Nov 24, 2022 at 4:23
  • \$\begingroup\$ MC14553B has been EOL for a while. I'm surprised t that they can still be had. \$\endgroup\$ Nov 24, 2022 at 4:30
  • \$\begingroup\$ The ICM7217 4 digit decade counter might be a good option. digikey.com/en/products/detail/rochester-electronics-llc/… \$\endgroup\$
    – PStechPaul
    Dec 3, 2022 at 5:00

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