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I am trying to design an LDO with the following specification: Vout = 1.5V; Vin = 1.7V - 2V; Iload = 75uA to 1200uA. However, while I am simulating its loop gain, its gain is coming negative. Even though all the transistors are in saturation within the given load condition. I have attached the testbench as well as the Bode Plot for it. Can anybody suggest what might be the reason?Testbench for AC analysisOutput of AC analysis

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  • \$\begingroup\$ That's not a negative gain, it means your output AC signal is less than 1V. Gain is a ratio. Please add the plot of V(out)/V(in) \$\endgroup\$
    – Designalog
    Commented Nov 25, 2022 at 8:36
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    \$\begingroup\$ Your schm is a bit poorly drawn, but from what I can see, there's no negative feedback. It don't see the middle point of your R1 and R2 network connected to either input of your amplifier. \$\endgroup\$
    – Designalog
    Commented Nov 25, 2022 at 8:38

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