I'm using an L78L33 with the TDMS442 (looks like the part is from 2007).

According to the L78L datasheet, it's recommended to use a 330 nF cap on the input and 100 nF on the output. I guess since these are small values that they are intended as decoupling caps rather than bulk caps?

Recommended L78L design

I read in TI's HDMI guide that you should use a 1 μF to 10 μF tantalum bulk cap on the output of the voltage regulator (page 12 on the HDMI guide). This guide is written around the TMDS341A, but I'm assuming it applies to all of TI's HDMI parts around that time (the guide is also from 2007).

I'm wondering if a tantalum is really needed. I read that in the early 2000's tantalums were often recommended over ceramic, but is that still the case? Would a ceramic cap suffice for this application?

L78L with added caps

Following TI's advice, I added the recommended bulk cap on the voltage regulator output, but while studying many other schematics that use voltage regulators, I noticed that the bulk cap is sometimes only on the input, so I added one there too.

Aside question: Is having a bulk cap on both the input and output necessary? I'm guessing it depends on the application. I suppose that an input bulk cap would help with supply dips, and an output bulk cap would be useful for when supplied components take gulps of power.

Primary question: Is it necessary to have decoupling caps there as well as the bulk caps, or would it be sufficient to only use bulk caps since I have local decoupling caps near the IC?

A similar thread answers the question on cap values, though the topic of having both smoothing caps and bulk caps isn't discussed there as far as I can see.

By the way, I have also used small decoupling caps near each VCC on the IC (0.1 μF to 0.01 μF) as directed by the datasheet. From memory, 19 decoupling caps in total for the IC. These are on the back of the board behind the IC due to limited space on the front caused by the high speed differential pairs. It’s a 4 layer board with ground on 2nd, power on 3rd, and low frequency traces on the back.

Edit: Below is what it looks like behind the IC. I added some larger bulk caps in the middle based on bobflux's advice.

Caps behind IC

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    \$\begingroup\$ As an aside, the 78L33 is a bad choice here - it's dropout voltage is >2V, so you would need a minimum 5.3V input supply. It's also a very old part with many much better modern options available. \$\endgroup\$ Commented Nov 26, 2022 at 12:35
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    \$\begingroup\$ You are using the wrong terms which is why you have not found many similar threads. A smoothing cap is for something like after a bridge rectifier to turn rectified AC into DC. That is actually smoothing. What you are talking about is called decoupling capacitors to combat voltage transients (whether up or down) due to current changes through trace inductance. "Bulk" is fine because it is one type of decoupling, but it is not bulk vs smoothing. This has been asked many times on this SE. Here are just some similar threads answered by me alone, let alone other people. \$\endgroup\$
    – DKNguyen
    Commented Nov 26, 2022 at 15:13
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    \$\begingroup\$ electronics.stackexchange.com/questions/639189/…, electronics.stackexchange.com/questions/566921/… \$\endgroup\$
    – DKNguyen
    Commented Nov 26, 2022 at 15:14
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    \$\begingroup\$ At the high speeds involved with HDMI, you're going to be more concerned about the parasitic inductance of your capacitors than their resistance. So not only should you use ceramic capacitors, you should look at the self-resonant frequency of those ceramic capacitors, as they're not very useful above that frequency. \$\endgroup\$
    – Hearth
    Commented Nov 26, 2022 at 18:05

1 Answer 1


L78L33 has a dropout voltage of 2V typical so it won't work with 5V input at 3V3 output. You need a low dropout regulator which can handle the current drawn by your load.

The HDMI guide linked in the question gives a quick summary on decoupling, but perhaps it is a bit too quick...

This sort of high speed chip will draw high frequency supply current, so it needs a low inductance power supply to avoid excessive HF supply noise, ripple and voltage drop that could bring the supply voltage out of the specified range. This is usually done either by placing one low value decoupling capacitor on each power pin (with good connection to the ground plane) or by using ground and power planes with enough capacitors spread around to create distributed capacitance and low impedance. Since the main point about these caps is to have low inductance, they should be physically small. In addition, there can be a lot of them, so they have to be cheap. So you will usually end up with a bunch of low value caps, like 10-100nF.

Ground and power plane (if any) should be solid, no cuts, no traces in the ground plane, etc. Planes have very low inductance because each trace or power plane is right next to the ground plane which makes a tight loop for the current. If there are cuts in the ground plane, current can take the long way around the cut, increasing inductance and emissions.

Anyway, you have a a number N of 10-100nF caps, in parallel. So you calculate the actual capacitance (including drop due to voltage) and then check if your LDO will be happy with that according to its minimum capacitance requirements. Note these MLCCs in parallel will have very low ESR, so you should pick a LDO that is stable with ceramic caps. If its datasheets asks for a special snowflake tantalum capacitor with a special value of ESR, check a more modern LDO, for example LDL1117.

Now you might want to add bulk capacitance for several reasons:

  1. the total value from the bunch of small caps may be too small to meet the LDO's minimum capacitance spec

  2. you want a better transient response: LDO's impedance will rise with frequency, so even if the capacitance value is enough to keep it stable, it may still be too low, and there may be a spot in the frequency range around 20-200kHz where the impedance is too high so you need more capacitance to lower it.

In this case you need more capacitance. Since everything has inductance the new capacitor will form a resonant LC circuit with the other caps. If you add a MLCC then its low ESR may make this resonance underdamped which leads to ringing and an antiresonance peak in the power supply's impedance seen by your chip. This can be countered either by using caps with several ohms ESR (general purpose aluminium/tantalum) which also increases power supply impedance, using caps with "just right" amount of ESR (like 100-200mOhms, but you'll end up with a large value cap if you use aluminium) or not leaving too much space between the values of MLCCs like 100nF-1µF-10µF.

enter image description here

It's all about what happens at the crossover frequency where the LDO's output impedance meets the cap's impedance. Here I have modeled various LDOs using series R+L, and added various caps, the plots are output impedance. It is best to avoid the one with the big spike.

You can test the transient response with a MOSFET switching a load resistor and a square wave, at various LDO idle currents. Or you can use a network analyzer, or simulations, but these are difficult to do if you don't have measurements or a spice model for the LDO.

Personally... I count 19 VCC pins and 19 GND pins, so if I put one cap between each GND/VCC pair on top layer that will not leave much room for traces. There are two pins between each GND/VCC pair, and routing two traces between the pads of a MLCC is n't ideal either. So I'd go with 4 layers, ground plane on layer 2, and put the caps below the chip. I'd put a power island on layer4 below the chip and a ground pour on layer3 to get good coupling between the two. Then all the pins would connect with vias on the inside of the footprint, leaving plenty of room for traces on the outside. Vias do have inductance, but considering the footprint, a trace to a cap that has to be a bit further away due to layout constraints will also have inductance. So now we have 19x 10nF caps which makes about 150nF, just add 1µF and 10µF in the center, and a LDO that will work well with 10µF ceramic cap like LDL1117. Then you can probably remove half the 10nF caps. If 100nF are used instead of 10nF, then the 1µF cap can be omitted.

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    \$\begingroup\$ You'll have vias for the chip's power and ground pins, considering how many there are already I'm not sure adding ground stitching vias would bring anything extra, besides making holes into the power "miniplane"... well you can always add some on the periphery. \$\endgroup\$
    – bobflux
    Commented Nov 27, 2022 at 13:30
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    \$\begingroup\$ Since the outer layers are only 0.2mm apart on standard 4 layer, the power island and its associated ground island on layer 3/4 will have much lower inductance than if they were on layers further apart ; also the copper is closer to the capacitors so the vias will have less inductance, which means you get lower resonance between your caps. If you don't need the layers for routing under the chip it has quite a lot of advantages. \$\endgroup\$
    – bobflux
    Commented Nov 27, 2022 at 13:32
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    \$\begingroup\$ That's likely, but footprints are free, so I'd put all 19 of them (if it fits without compromises) then populate them all, or half, depending on what the measurements say (noise and ripple on a chip supply pin). \$\endgroup\$
    – bobflux
    Commented Nov 27, 2022 at 16:45
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    \$\begingroup\$ Looks good. For the 4 larger value caps you should give each its own pair of vias for lower inductance. Vias to the side of the cap (like on the 19 caps) result in shorter traces and lower inductance than vias on the ends (like on the 4 caps). \$\endgroup\$
    – bobflux
    Commented Nov 27, 2022 at 19:21
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    \$\begingroup\$ Great! Will do. Thanks. \$\endgroup\$ Commented Nov 27, 2022 at 21:39

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