At 1kHz, switching loss is essentially irrelevant, even with fairly lax drive. That means switching times (notice the generator resistance RG or RGEN they are specified with) and gate charge are unimportant.
That said, the 12 to 27kΩ drive is ponderously slow, for no obvious reason. Consider a circuit like this:
(Image source: CircuitDen | Artin Isagholian - Discrete Gate Driver Designs, Design 1 (Low Current))
Note that R1 is equivalent to your R3. The zener can be placed on the same node (Q2 collector) to limit gate voltage if needed. The diode (a smaller type like BAT54 or BAT85 can be used) allows Q2 to pull down the gate, discharging faster than a resistor alone, while saving transistor count. (Not that it matters much, transistors are quite cheap.) Meanwhile, Q1 acts to multiply R1's current, by its hFE roughly, thus a 10k pullup looks like ~100Ω to the gate.
I'm guessing low current consumption isn't much of a problem, given the shunting mode output, so additional savings aren't really necessary. If they were, options would include CMOS level shifters/drivers, reevaluating the current source (use a lower sense voltage? use a more efficient SMPS?), and perhaps using power-saving modes in the MCU and any other peripherals (most of these being well beyond the scope of this particular question).
Edit: another example for the "it pays to actually calculate" bin!
The gate voltage rise/fall is very slow. Qg(tot)(max) = 3 or 6nC at 5V, respectively. The gate is a nonlinear capacitance, but we can approximate it as an average equivalent by simply dividing total charge by the voltage swing. This gives 1.5 or 3nF average gate capacitance Ciss(avg).
Against 12k (falling) or 27k (rising), that capacitance will have a time constant of 27 to 162µs. Versus a ~500µs half-period at 1kHz -- and worse for any duty cycle other than 50%, that's a huge amount of time spent in the transition, in comparison.
Now, the full risetime (10-90%) will be about 2.2 times the RC time constant, but also, the bulk of the actual switching occurs in a fraction of this -- about QGD, or for these transistors, about a third of the total. So it's not quite as bad as it sounds, but it also means there will be distortion (actual pulse width at the LEDs different from what's driven) near the extremes, as the on or off period approaches this time. So, for duty cycles outside of say 20-80%, it's not looking great.
Using a 10k pullup with hFE = 100 follower would give a modest rise of 150-300ns, slow enough not to be an EMI concern, yet fast enough to give reasonable duty range.
The pull-down transistor (Q2 above, Q1 in the original) should be driven hard enough to pull down the gate in reasonable time; not much static pull-down is needed, but a series resistor and capacitor can be wired in parallel with your R1, say 220R + 2.2nF, to greatly increase turn-on current without increasing DC consumption. (A discharge path will also be needed: connect a signal diode (BAT54, BAT85, 1N4148, etc.) from GND (anode) to Q1 base (cathode) to do this.)