I have a round surface of 1.5 meters in diameter that contains many electronics. What I would like to do is distribute a 10MHz 3.3V clock signal from Teensy 4.0 across the table for 200 ADCs to access it. The ADCs are placed evenly across the whole round surface. It sounds crazy, I know, but there are many limitations to this system that make me consider it. What would be good options for creating such a clock grid?

Some background information: The issue started with the fact that I need the 200 ADCs to work synchronously by using an external clock (preferably, from the Teensy 4.0) instead of their internal clock. I tried to supply this clock signal to one of the ADCs at a distance of 1.5m and the signal was very ugly and ringing because of the inductance and capacitance of the wire. Also, I saw a reflection of the clock signal because the impedances are not matched, hence, the 10MHz wire acts as a transmission line. For this measurement, I used a regular ribbon wire. I learned that it would be much better to use a shielded cable, such as CAT5 or CAT5E. However, the space is very limited for this surface, and I also need to supply 200 modules with a sufficient clock signal. I looked into the option to use M-LVDS (Multidrop), however, I have concerns that there might be better-suited options to look into that I have not thought of.

Any comments and ideas would be much appreciated. Please let me know if I should provide any additional information.

  • \$\begingroup\$ What's the environment that whatever it is you are building is supposed to sit in? \$\endgroup\$
    – Lundin
    Commented Nov 29, 2022 at 12:47
  • \$\begingroup\$ How are they going to be wired for data? How simultaneous do they have to be? Are they daisy-chained? (presumably the teensy doesn't have 200 data ports). Are you doing your own PCBs? \$\endgroup\$
    – pjc50
    Commented Nov 29, 2022 at 12:48
  • \$\begingroup\$ Have you googled "clock distribution" or "clock driving" ? There's a host of products and application notes out there. \$\endgroup\$ Commented Nov 29, 2022 at 12:50
  • \$\begingroup\$ Can you give more details like what ADC chip is used, what sample rate, and how all the ADCs are wired to the master? Does the ADC have a pin to trigger sampling, or do you absolutely have to use the clock? In the latter case you will also need to trigger sampling at the same time on all ADCs so you have two signals to distribute accurately... \$\endgroup\$
    – bobflux
    Commented Nov 29, 2022 at 12:58

2 Answers 2


It depends a lot on how the 200 ADCs are actually built and wired up.

Offhand I would suggest a master clock driver driving a number (maybe 5 or 10) of coax or twisted pair wires in a star configuration followed by whatever secondary distribution you need to get it to the individual ADCs.

You can regenerate and de-jitter the clock signals local to the ADCs with PLL clock generator chips, so you'd be distributing a synchronization signal rather than directly distributing a clock where jitter and such like may directly affect your ADC measurements unfavorably.

  • 2
    \$\begingroup\$ +1 for using the main distribution only for synchronisation. That way, you can distribute a high-jitter, but low-bandwidth (e.g. sine wave) clock at any frequency that is non-offensive to your actual measurement, then use local PLLs to supply a synchronous low-jitter 10 MHz to several nearby ADCs \$\endgroup\$
    – tobalt
    Commented Nov 29, 2022 at 13:07
  • 3
    \$\begingroup\$ Suspect an XY problem where OP has conceived a solution difficult to implement. And Spehro's suggestion somewhat un-winds this solution. Perhaps further un-winding may come up with an even better approach - a more detailed spec from the OP would be required. \$\endgroup\$
    – glen_geek
    Commented Nov 29, 2022 at 15:24

Your current description lacks a lot of application detail but it appears the 10 MHz is the ADC conversion clock. Transmitting that from a single source into a high fan-out like 200 ADCs requires lots of parallel buffers, each of which will introduce skew (constant) and jitter (dynamically varying) between the clocks. So you need to consider how much your system can tolerate to work out if the design is practical.

You would probably have more success by distributing a HEARTBEAT pulse to each of the 200 ADC circuits. Each ADC circuit would be a sample and hold and ADC. The HEARTBEAT (or whatever it's named) pulse can switch the sample and hold to acquire then trigger an ADC conversion.

If you must have sample-and-hold within the ADC, HEARTBEAT can trigger an ADC controller circuit using a cheap FPGA such as an ice40. Using a 200 MHz clock from an internal PLL, this would have 5 ns max. jitter in detecting HEARTBEAT then read the ADC at a divided-down frequency and transmit it back.

The interfaces should use a differential standard, such as LVDS. Many/most FPGAs have LVDS transmitters and receivers capability for their I/O pins. These will suit a contained short distance application like that you describe.

Your Host controller is going to need a lot of inputs to receive 200 data streams in parallel. FPGA(s) would handle that well, too.


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.