I playing with JFET Common Source amplifier with feedback loop. I am simulating the design showed here. https://www.ti.com/lit/an/slpa018/slpa018.pdf?ts=1669662908797&ref_url=https%253A%252F%252Fwww.google.com%252F

I followed the steps for feedback stability analysis (breaking the loop, inserting the inductor and cap etc.) I get from simulator the same results as are presented in the paper. What I am not sure about is phase margin evaluation. The phase of the circuit starts at -90 deg and at point when gain is 0 is -266 deg. I thought that the phase margin of this circuit is than just 4 degree (-266 + 90 = -176, 4 degree to -180). They are claiming that the phase margin of the circuit is 87.4 deg (page 8 in attached paper).

Could me someone explain what is right phase margin of the circuit and what is proper calculation?
Standard schematic Standard schematic Stability analysis schematic Stability analysis schematic Simulation Simulation

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  • \$\begingroup\$ Isn't is a common gate circuit? \$\endgroup\$
    – Andy aka
    Nov 30, 2022 at 13:41
  • \$\begingroup\$ I added the standard schematic in which amplifier operates. \$\endgroup\$ Nov 30, 2022 at 13:55

1 Answer 1


Peter, I agree with you. The comments to the phase margin measurements are confusing - more than that: To me, the comments are really wrong. I think, they have applied not the correct definition for the phase margin. (Sorry to say - you have made a similar error).

Let me explain: Sometimes there is a confusion in the phase margin definition because - unfortunately - in the literature, there are two different definitions for loop gain:

1) Loop gain is the product of all gains within the loop - WITHOUT taking into account the sign inversion(s) at the summing node resp. within the loop.

2) Loop gain is the gain which can be measured, calculated or simulated by opening the loop at a suitable point and inject a test signal (as you did, with an inductor because of the DC operating point). In this case, of course all sign inversions within the loop are taken into consideration.

Phase margin:

  • case 1): The critical phase (at zero magnitude) is -180 deg
  • case 2): The critical phase it at -360 deg (identical to zero deg).

Therefore, in the case under discussion the phase margin is PM=360-267.4=92.6 deg.

  • \$\begingroup\$ But what about initial phase ? Shouldn't I somehow take into consideration that the phase already starts at -90 deg ? And one additional question. Which points are suitable for the breaking the loop ? \$\endgroup\$ Nov 30, 2022 at 15:35
  • \$\begingroup\$ Normally, the phase must start at -180deg (neg. feedback). However, due to simulation with Cd (highpass) the phase starts at -180+90=-90 deg. Thats OK - and this has no influence on the applicability of the criterion: Stability limit at unity loop gain (unity magnitude and zero phase). When you are using an inductor and a coupling-C the selection of a suitable point is uncritical. As an alternative, you could use a test voltage source directly at the opamp output BETWEEN the output node and the first node called VF1 \$\endgroup\$
    – LvW
    Nov 30, 2022 at 15:58

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