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I am aware of some basic goals of a decoupling and grounding layout: Reduce EMI by minimizing overall power-GND high-frequency current loop area, minimize ground inconsistency by reducing impedance to GND connections, keep high frequency current from going to other devices.

These goals have led me to a dilemma between two layouts, both of which I can find support for in previous answers to questions.

Option 1: Only connect a single via to GND plane

Olin Lathrop Single Ground Via

Pros: Hi-frequency loop currents are kept off of GND plane.

Cons: IC GND pin to GND plane connection may have too much inductance. Oscillator capacitors may be ineffective due to long distance from GND via.

Advocated here: Competing PCB Crystal layout recommendations Decoupling caps, PCB layout

Option 2: Place GND connections as close as possible to GND pads Many GND Vias Layout

Pros: Low-inductance ground plane connection for all caps and the IC.

Cons: According to the above links, this creates a "Center-fed patch antenna" which will radiate EMI and pollute the ground plane with high frequency currents.

Advocated here: Which of these layouts for decoupling capacitors attached to an IC is wrong?

Board details

This is a 4 layer board with internal VDD and GND planes.

IC U1 is the Microchip MCP3425. Y1 is a 20 MHz oscillator. The IC outputs 1Mhz CAN Bus signal and 20 KHz SPI signal.

C1 = 0.01 uF IC bypass cap. C2 = 0.1 uF IC bypass cap. C22 = 10 uF local Feed point decoupling cap. Y1 = crystal oscillator. C8 and C9 = 22pF oscillator caps.

Edit 1 PCB Stackup The PCB is currently TOP SIGNAL-GND-5V-SIGNAL BOTTOM, and it is a single sided design, so the bottom signal layer has no components, just routing signals. The TOP signal layer is 1.5mil from the GND plane.

Which layout is more effective for decoupling and grounding?

EDIT 2 Option 3 Here I have incorporated some of the feedback below. Each cap now has its own via to GND plane placed close by. Extra vias are added to lower inductance. The GNDs are all still connected on top to reduce ground bounce.

Version 3, lots of GND vias

EDIT 3 OPTION 4 Based on BobFlux's answer with decoupling cap by VDD. Pros: Decoupling cap is by VDD as expected. BobFlux idea with Cap by VDD

OPTION 5

I'm not sure if putting the decoupling cap next to the GND pin is frowned upon, does anyone have thoughts? I really like how there's only 1 GND via on the IC's power loop, every GND connection has an immediate adjacent via, and al the GND vias are fairly close together so GND plane "Patch antenna" effects should be reduced: BobFlux Idea

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    \$\begingroup\$ I don't personally like #1 at all. The inductance is higher (as you say), but also any return current from the digital outputs take a potentially strange path to the chip. If you have mixed analog and digital you really want to get to a ground plane as directly as you can, not route around two different layers along the way. \$\endgroup\$ Commented Dec 1, 2022 at 4:28
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    \$\begingroup\$ I think you will like these: signalintegrityjournal.com/blogs/12-fundamentals/post/… and youtube.com/watch?v=Fj9M2CK2cX0 \$\endgroup\$
    – RemyHx
    Commented Dec 1, 2022 at 7:46
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    \$\begingroup\$ I almost always make a SIG-GND-GND-SIG stackup, route the power. Practically only use the 22uF suggestion of Bogatin (links above). In most use cases the usage of two or three cap's at the Vcc is legacy thinking. I use a lot of GND via's, next to signal transitions and via stitching. So the first one I really wouldn't use. Let me turn around the suggestion: if gnd plane poisoning would be a problem, what to do with all those signals? Making separate planes? \$\endgroup\$
    – RemyHx
    Commented Dec 1, 2022 at 7:51
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    \$\begingroup\$ NB: where do your signals on the power plane side return? It is potentially possible to use the power plane as a reference, but if those signals cross planes from 1->4 or back, you induce emi problems. \$\endgroup\$
    – RemyHx
    Commented Dec 1, 2022 at 7:56
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    \$\begingroup\$ signalintegrityjournal.com/articles/… \$\endgroup\$
    – RemyHx
    Commented Dec 1, 2022 at 17:53

3 Answers 3

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I drew the chip and bondwires in white.

enter image description here

Assuming ground plane on layer2, ground via (green) on the inside of the ground pin lets the ground return current pick the shortest path right under the bondwire (green, dashed) to the cap (left). +5V via in red.

This alternate layout ensures all HF currents from this chip enter the ground plane at the single ground via near the ground pin:

enter image description here

The +5V trace runs under the bondwire and chip to minimize inductance.

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  • \$\begingroup\$ Wow I'm impressed. The power and GND pins being opposite made it hard to follow both schools of thought ("Minimize inductance of all ground connections" VS "Keep HF currents off GND plane by connecting to GND at a single point"). But you did it by placing the decoupling CAP by the GND pin instead of VDD \$\endgroup\$
    – Luminaire
    Commented Dec 3, 2022 at 23:26
  • \$\begingroup\$ Your points about the bond wires inside the package are really helpful, I hadn't even thought of that. \$\endgroup\$
    – Luminaire
    Commented Dec 3, 2022 at 23:26
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    \$\begingroup\$ If you put the cap on GND pin you'll have to route VCC with a trace, it can be annoying if you have other traces under the chip. If you put the cap on VCC pin then the ground current goes through the plane. The latter has lower total inductance, because the plane has lower inductance than the trace. But the cap on GND pin keeps ground plane cleaner. It's similar to doing the layout for a DC-DC converter, think about loops. \$\endgroup\$
    – bobflux
    Commented Dec 3, 2022 at 23:41
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    \$\begingroup\$ Note if the chip has this footprint then it will be designed to be absolutely fine with the extra inductance in its power supply due to distance between power and ground pin. It's the worst case pinout because the bond wires and leadframe wiring for VCC and GND are the longest. When you see a chip has many VCC/GND pins, in pairs, close together, it's a sign it really needs low inductance power supply. \$\endgroup\$
    – bobflux
    Commented Dec 3, 2022 at 23:44
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    \$\begingroup\$ I think unless you have sensitive analog components nearby you'd be fine with any of the options but 4 and 5 are my favorites ;) The worst case would be a 2 layer board with lots of traces in the "ground plane" so the current in the cap has to take the long way around. \$\endgroup\$
    – bobflux
    Commented Dec 4, 2022 at 7:45
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Option 1: Only connect a single via to GND plane Pros: Hi-frequency loop currents are kept off of GND plane.

Yeah, but you made yourself a nice antenna. The most effective grounding schemes allow return currents to flow back to the source. The best way to do this is to make everything connected to ground low impedance. The other problem with this scheme is the one via. The capacitance between them is in the pfs range the via inductance is in the nH range, that makes an LC resonator in the GHz range (which might be a problem if you have harmonics). Ground the plane on both sides and the antenna mostly goes away and you halve the inductance for any currents that need to return to ground.

Option 2: Place GND connections as close as possible to GND pads

Is good, way better than the other option. the current from any source has one inductor which lessens the common mode voltage created by currents traveling through inductors from affecting the ground plane.

The best thing would be a combination of both, but probably overkill for most applications. In the least, putting a shield around the oscillator reduces stray fields and offers a low inductance pathway back to the source.

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  • \$\begingroup\$ Thank you for your detailed response. I see you are on team "Everything connect to ground low impedance." Your reasoning makes sense. How would you respond to this answer that says one via is best? electronics.stackexchange.com/questions/15135/… \$\endgroup\$
    – Luminaire
    Commented Dec 3, 2022 at 21:43
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    \$\begingroup\$ I don't agree with that statement, the more vias the better, what really matters is where the currents are going. You can easily model the plane in spice and see the is a higher voltage on the plane with only one via, and it also has a higher resonance point. Two vias well lower the impedance by half, which will cut the voltage in half. You might have issues with LC resonance response but that can be calculated. RF boards stich planes together with many vias to lower radiation. \$\endgroup\$
    – Voltage Spike
    Commented Dec 3, 2022 at 23:49
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It is never enough to say "I have internal Power and GND planes"!

It all depends on your internal plane spacing. Say if you have GND on L2, then the second layout is probably really good, because the loop inductance will be low.

If however GND is on L3 or even more bottom layer (with other layers in between), then option 2 will be disastrous! And then option 1 could be actually better, although even in this case it will be yet better if you leave the L1 connection and the Vias - it keeps a large common-mode voltage from developing on the dangling copper antenna and reduced EMI issues.

You also note that one layout "keeps HF loop currents off of GND plane" as a pro. IMO, the GND plane is not a bad place at all for those currents. You use a contiguous plane, precisely to allow for all sorts of such currents to roam freely. If there were no currents in your plane, you could omit it after all. It is MUCH(!!) more important to keep parasitic currents off of places where they actually matter, e.g. signal lines. See below.

Your specific layout

You have GND in L2 very tightly stacked near L1, so using GND for L1 return currents will provide excellent performance. This is good for routed signals and power on L1.

However your Power on a very far away L3 is a very often made erroneous (IMO) design decision. It doesn't directly affect the local IC decoupling you are asking about because the IC has a local power source on L1. But all of the power distribution currents will run through those planes. Due to the large gap between L2 and L3, these supply currents will not induce return currents in eachother (reducing inductance), but will instead induce parasitic return currents in L1 and L4, where your signals are. This will impact your signal integrity and will worsen EMI performance.

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  • \$\begingroup\$ That makes a lot of sense. The farther GND is from the signal layer, the more signal loop area when using the GND plane. So different layouts might be superior depending on plane stackup. I edited the question and added the layer stackup. \$\endgroup\$
    – Luminaire
    Commented Dec 3, 2022 at 20:46
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    \$\begingroup\$ @Luminaire I have added some comments on your stackup. \$\endgroup\$
    – tobalt
    Commented Dec 4, 2022 at 5:23
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    \$\begingroup\$ OK, yes GND planes are a reasonable place for HF currents. So the goal is to get supply and return current paths closely aligned to each other. Then HF currents easily cruise in each other's magnetic wake. Almost like drafting in NASCAR? But since the L2 GND plane is closer to L1 signals and far from L3 VDD supply currents, it's return currents are going to make turbulence with signals on closer L1, instead of neatly drafting with far L3. Does that sound right? So solutions might be turning L3 into GND and routing VDD on L1? Or moving L3 to be close to L2 if my fab allows it? \$\endgroup\$
    – Luminaire
    Commented Dec 5, 2022 at 17:19
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    \$\begingroup\$ @Luminaire Yes I think I agree about basically everything you wrote. As most standard 4-layer stackups have a large gap between L2 and L3, I am a fan of having both these layers GND planes and I route power in L1 and L4, much like signals, but with wider copper patches/traces. \$\endgroup\$
    – tobalt
    Commented Dec 5, 2022 at 17:34

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