VDD pin is opposite from GND pin. Which layout is more effective for decoupling and grounding?

Question

I am aware of some basic goals of a decoupling and grounding layout: Reduce EMI by minimizing overall power-GND high-frequency current loop area, minimize ground inconsistency by reducing impedance to GND connections, keep high frequency current from going to other devices.

These goals have led me to a dilemma between two layouts, both of which I can find support for in previous answers to questions.

Option 1: Only connect a single via to GND plane

Pros: Hi-frequency loop currents are kept off of GND plane.

Cons: IC GND pin to GND plane connection may have too much inductance. Oscillator capacitors may be ineffective due to long distance from GND via.

Advocated here: Competing PCB Crystal layout recommendations Decoupling caps, PCB layout

Option 2: Place GND connections as close as possible to GND pads

Pros: Low-inductance ground plane connection for all caps and the IC.

Cons: According to the above links, this creates a "Center-fed patch antenna" which will radiate EMI and pollute the ground plane with high frequency currents.

Advocated here: Which of these layouts for decoupling capacitors attached to an IC is wrong?

Board details

This is a 4 layer board with internal VDD and GND planes.

IC U1 is the Microchip MCP3425. Y1 is a 20 MHz oscillator. The IC outputs 1Mhz CAN Bus signal and 20 KHz SPI signal.

C1 = 0.01 uF IC bypass cap. C2 = 0.1 uF IC bypass cap. C22 = 10 uF local Feed point decoupling cap. Y1 = crystal oscillator. C8 and C9 = 22pF oscillator caps.

Edit 1 The PCB is currently TOP SIGNAL-GND-5V-SIGNAL BOTTOM, and it is a single sided design, so the bottom signal layer has no components, just routing signals. The TOP signal layer is 1.5mil from the GND plane.

Which layout is more effective for decoupling and grounding?

EDIT 2 Option 3 Here I have incorporated some of the feedback below. Each cap now has its own via to GND plane placed close by. Extra vias are added to lower inductance. The GNDs are all still connected on top to reduce ground bounce.

EDIT 3 OPTION 4 Based on BobFlux's answer with decoupling cap by VDD. Pros: Decoupling cap is by VDD as expected.

OPTION 5

I'm not sure if putting the decoupling cap next to the GND pin is frowned upon, does anyone have thoughts? I really like how there's only 1 GND via on the IC's power loop, every GND connection has an immediate adjacent via, and al the GND vias are fairly close together so GND plane "Patch antenna" effects should be reduced:

Answer 1

I drew the chip and bondwires in white.

Assuming ground plane on layer2, ground via (green) on the inside of the ground pin lets the ground return current pick the shortest path right under the bondwire (green, dashed) to the cap (left). +5V via in red.

This alternate layout ensures all HF currents from this chip enter the ground plane at the single ground via near the ground pin:

The +5V trace runs under the bondwire and chip to minimize inductance.

Answer 2

Option 1: Only connect a single via to GND plane Pros: Hi-frequency loop currents are kept off of GND plane.

Yeah, but you made yourself a nice antenna. The most effective grounding schemes allow return currents to flow back to the source. The best way to do this is to make everything connected to ground low impedance. The other problem with this scheme is the one via. The capacitance between them is in the pfs range the via inductance is in the nH range, that makes an LC resonator in the GHz range (which might be a problem if you have harmonics). Ground the plane on both sides and the antenna mostly goes away and you halve the inductance for any currents that need to return to ground.

Option 2: Place GND connections as close as possible to GND pads

Is good, way better than the other option. the current from any source has one inductor which lessens the common mode voltage created by currents traveling through inductors from affecting the ground plane.

The best thing would be a combination of both, but probably overkill for most applications. In the least, putting a shield around the oscillator reduces stray fields and offers a low inductance pathway back to the source.

Answer 3

It is never enough to say "I have internal Power and GND planes"!

It all depends on your internal plane spacing. Say if you have GND on L2, then the second layout is probably really good, because the loop inductance will be low.

If however GND is on L3 or even more bottom layer (with other layers in between), then option 2 will be disastrous! And then option 1 could be actually better, although even in this case it will be yet better if you leave the L1 connection and the Vias - it keeps a large common-mode voltage from developing on the dangling copper antenna and reduced EMI issues.

You also note that one layout "keeps HF loop currents off of GND plane" as a pro. IMO, the GND plane is not a bad place at all for those currents. You use a contiguous plane, precisely to allow for all sorts of such currents to roam freely. If there were no currents in your plane, you could omit it after all. It is MUCH(!!) more important to keep parasitic currents off of places where they actually matter, e.g. signal lines. See below.

Your specific layout

You have GND in L2 very tightly stacked near L1, so using GND for L1 return currents will provide excellent performance. This is good for routed signals and power on L1.

However your Power on a very far away L3 is a very often made erroneous (IMO) design decision. It doesn't directly affect the local IC decoupling you are asking about because the IC has a local power source on L1. But all of the power distribution currents will run through those planes. Due to the large gap between L2 and L3, these supply currents will not induce return currents in eachother (reducing inductance), but will instead induce parasitic return currents in L1 and L4, where your signals are. This will impact your signal integrity and will worsen EMI performance.