I want to figure out the maximum continuous average power I can get from a MOSFET from the "Maximum Safe Operating Area" graph. For my example case, I chose CSD19535KTT (just because the data-sheet is good and my application will be high power):

CSD19535KTT safe operating area

I will be operating in the saturation region with 10us pulses, Vds at 70V and a load which draws 400A current. So my instantaneous power per pulse is 28000 Watts. Also, as per the graph I should not be in thermal instability region in any way. Also assume I want to operate at roughly room temperature (25°C).

1. What confuses me is the term "Single pulse" in the graph - Are we talking about continuous 10us pulses at 50% duty cycle or one pulse in a long time? - The reason I ask is that 28000*0.5 W = 14 kW from a single MOSFET doesn't seem realistic.

As per the data-sheet the following are the absolute maximum ratings:

Drain-to-Source Voltage : 100 V
Gate-to-Source Voltage  : ±20 V
Continuous Drain Current TC=25°C : 197 A
Continuous Drain Current TC=100°C : 139 A
Pulsed Drain Current : 400 A
Power Dissipation, TC = 25°C : 300 W

The Vds of 100V and pulsed drain current of 400A are clear from the graph. What I don't understand is - 2. What does the "Power Dissipation" rating mean and how does it relate to the graph?. If the power dissipation rating is the continuous average power the MOSFET can operate in, then can some please explain how this 800VA inverter design can work with 150W MOSFETS?

3. Finally, how do I calculate my maximum duty cycle a the operating point I chose?

  • 4
    \$\begingroup\$ You are operating too close to the edge for this to be a reliable design. \$\endgroup\$
    – Andy aka
    Dec 1, 2022 at 12:17
  • 1
    \$\begingroup\$ @Andyaka Yes, I agree than I am too close to the edge. However, the question is more on how to calculate the continuous power available. If you want, you can take a more conservative operating point like 70V, 300A, 10us pulse. Even then the instantaneous wattage of 2.1 kW is too high. \$\endgroup\$ Dec 2, 2022 at 5:49
  • \$\begingroup\$ You can't use the SOA chart to determine the maximum allowable power dissipation. \$\endgroup\$
    – user57037
    Dec 3, 2022 at 20:06
  • 1
    \$\begingroup\$ Just to quickly double-check your application, can you confirm that during your 10 us pulses, the transistor will be conducting 400 Amps while simultaneously maintaining a drop from drain to source of 70 V? In other words, this is not a switching application? Because if you are turning the transistor fully on then Vds will be much lower than 70 V once the transistor is on. 400 A is a lot, even when fully on, but it may be possible with low duty cycle. \$\endgroup\$
    – user57037
    Dec 3, 2022 at 20:13
  • \$\begingroup\$ The SOA graph shows the max power when the device in is saturation mode. Assuming you're applying a sufficiently high gate voltage to fully turn on the device, Vds during saturation will be 3 V (using the Rds on limitation line in the graph). Texas Instruments has a video on understanding SOA. \$\endgroup\$
    – qrk
    Dec 3, 2022 at 21:05

4 Answers 4


Here is the simple version. I will mention the complications afterward. The maximum continuous average power dissipation is based on three things.

  1. R\$\theta\$JA (62 C/W from the datashseet)
  2. TJmax (175 C from the datasheet)
  3. Ta, the ambient temperature in the immediate environment of the transistor

You must not ever let the temperature of the silicon rise above TJmax. Not in storage and not in operation. There may be a brief exception for soldering (check the soldering profile).

R\$\theta\$JA means that for every Watt of power you dissipate, the silicon die will rise by 62 degrees above ambient.

The formula for silicon die temperature is:
Tdie = TA + R\$\theta\$JA x P
Where Tdie is the silicon die temperature, TA is the ambient temperature, and P is the power dissipated by the die (roughly VDS x IDS)

If you re-arrange that equation to solve for P, you can calculate the maximum power dissipation by substituing in 175 (TJmax) for the die temp, and put in a real number for TA.

For example, if the ambient temperature is 40 C, then the equation becomes:
P = (175 - 40) / 62 = 2.2 Watts
So the maximum average power dissipation is 2.2 Watts, assuming the ambient temperature is 40 C.

There are assumptions that go into calculating this power limit. The datasheet is assuming some standard PCB footprint is used and that there is no heatsink. It is possible to dissipate additional power by using extensive thick copper on the PCB. This will allow the transistor heat to flow into the copper and effectively use the PCB as a heatsink.

You can actually add a heatsink to the transistor case also. You can cool the heatsink with a fan, or even use liquid cooling.

So it is possible to dissipate much more than 2.2 Watts at 40 C. But it requires some effort.

The maximum power dissipation limit reported by the datasheet should only be used to compare with other transistors in the same package. It is kind of a figure of merit I guess you could say. Not a dissipation that you can obtain in practice, because it is not possible using ordinary design techniques to keep the case temperature at 25 C while dissipating 10 or 20 Watts. Even less so while dissipating 100s of Watts. In general, I never look at the maximum current rating nor the maximum power dissipation rating when selecting MOSFETs. I look at Rds(on) first, usually, because my goal is usually to minimize power dissipation due to conduction while the FET is on.

  1. Single pulse is just that, a single pulse. Enough time is spent between pulses that there's no evidence of the prior pulse. Namely that TJ returns to the 25°C specified in the conditions. This may be a duty cycle much less than 0.1%.

  2. Power dissipation is DC -- and at that, they don't often say so but this may be performed literally with the whole case at 25°C. This is achieved by immersing the part in a pool of boiling, nucleated* Freon. The full latent heat of the coolant is available to bring every point on the component surface to the rated temperature, even under extreme heat fluxes.

*That is, full of fine bubbles ready to expand into vapor.

It's not clear how often this technique is used. I recall an appnote back in the day which basically amounted to, "yeah we know this method is specsmanship and hopelessly unrealistic, but, they [competitors] do it, so we do it too". Or maybe it was actually AN-1140 and I've forgotten the context of the original document, or the surrounding conversation, from that long ago.

In any case, it's a shame that datasheets never discuss it, and appnotes rarely do. Presumably there are semiconductor standards set for it (by SEMI, JEDEC or other groups), but they are obscure, and not readily available or leaked online. Or even if they are, not knowing exact keywords to search for, they don't turn up on modern search engines which prioritize other kinds of material. In short, unless you're in the business, these standards are just about nonexistent.

Two which do mention the method are:
Application Note AN-1140, Continuous dc Current Ratings of International Rectifier’s Large Semiconductor Packages (International Rectifier), and
Semiconductor and IC Package Thermal Metrics (SPRA953C) (Texas Instruments).
These also seem to suggest the modern method is to use a fluid-chilled cold plate -- on the heatsink surface proper, not all over. A more realistic condition, representative of standard and recommended heatsinking practice.

In any case, the temp rise between junction and case, or case and heatsink and ambient, needs to keep TJ within limit. Simply add up the thermal resistances, multiply by power, and there is your temp rise.

There may be additional limitations, which AN-1140 goes into detail of. If bondwire, lead or package limits are specified, they must also be respected, and the die limit is essentially irrelevant and can be ignored. Note that any current limits are simply power limits, converted by element resistances. You don't need to know the wirebond diameter and material, or resistance, just its current limit.

And to be clear, what matters for this spec is average power, i.e. continuous, DC, over a long period of time. For pulsed operation, it averages out somewhat, and this is described by the transient thermal response plot (usually found in the datasheet). Data are given for continuous-pulsed operation (at given duty cycles, square pulses) and single (being by the same condition as before: TJ(initial) = 25°C or whatever).

It is perfectly reasonable for the chip to dissipate extreme amounts of power, for tiny fractions of a second; as long as TJ is respected even instantaneously (say, within ~µs), and then over time (ms to s), the heat eventually spreads out into the package and heatsink.

  1. Duty cycle can be calculated, or at least estimated, from the thermal impedance plots. Further reading: Power MOSFET Thermal Design and Attachment of a Thermal Fin (Toshiba)

Regarding the 800VA inverter, it uses class D operation. They simply never dissipate anywhere near 800W, at least for more than a fraction of a microsecond. The load line swings very rapidly between low voltage at high current, and high voltage at low current. Both extremes have little dissipation, and very little time is spent in the high-dissipation region inbetween.

That said, it's not clear what you intend to accomplish with your 70V 400A 10µs pulse, if anything at all. If these are the supply voltage and load currents, and you intend to operate in a switched mode, you are apparently ignorant of the above option. Perhaps you're making a fast electronic load or something, and the device dissipation is the point, I don't know. If you intend to build something like an inverter, this does not bode well for your success, and much learning is suggested before attempting a full scale (100s of W) design.

  • \$\begingroup\$ I was trying to design a high power ESC. I understand that the inductive load for motors and the transformer(in case of the inverter) will cause out of phase voltage and current thus reducing power load. However I wanted to keep the load independent of the design consideration. Guess I was wrong. \$\endgroup\$ Dec 5, 2022 at 18:04

You need to consider the power in the MOSFET differently.

The MOSFET, when off, has 70 volts from drain to source with a leakage current of 1 nanoampere, so during the "off" portion of your pulse, the MOSFET is dissipating 70 nanowatts. When on, your 2.8 milliohm on resistance at 400 amps yields 448 watts, not 28000 watts as you have suggested. This is too high for this part, as you can readily see by the very good explanation provided by @mkeith. I hope this helps you see how the 800VA design can work.

If the "on" and "off" contributions were the only ones, your average power for a 50% duty your average power would be 224 watts. But there is another significant contributor. The MOSFET does not switch "on" and "off" instantaneously, and during the actual rise and fall times, there is both voltage and current present, and this means power is being dissipated in the part. This is why you must design to make the MOSFET switch cleanly, because each edge contributes energy to the MOSFET that must be dissipated as heat. You can see that at higher frequencies, the edges occur more often, so that the power loss associated with the switching transients will be proportionally higher. High current MOSFETs have high gate capacitances, so gate drives must be high power with low inductance - you need large current paths and low inductance everywhere to keep the switch as clean as you can.

So in answer to your question, you can use the on resistance to get a start, but you will need to consider the rise and fall times and the switching frequency when estimating your power losses. Then mount to a large heat sink, and then apply the thermal resistance calculation.

Good luck!

  • \$\begingroup\$ If you perform a simulation, you can see that, during switching, the maximum power occurs approximately with half the peak current and half the peak voltage, so for the 400A and 70V, peak power will be about 200*35 = 7000 watts. This would be equivalent to 70 watts continuous for a 1% duty cycle, so if your PWM is 10 kHz (100 uSec period), the total MOSFET switching time should be less than 500 nSec. My calculation is a worst case estimate, as the average power during switching is probably less than half the peak power. This power is in addition to the power dissipated during the ON time. \$\endgroup\$
    – PStechPaul
    Dec 9, 2022 at 21:52

You cannot do what you expected. The current does not shut off instantly. It must be quenched or decay slowly with the exponential turn-off time from T=L/R to 36% Vdd and major LC resonances from the gate and drain charges as the Ron rises to increase Q.

Qg Gate Charge Total (10 V) 75 nC
Qgd Gate Charge Gate-to-Drain 11 nC

This is equivalent at Vgs = 0 V, Vds = 50 V, ƒ = 1 MHz ;
Ciss Input capacitance . . . . . . . . . . 6100 ~ 7930 pF . (typ ~ max)
Coss Output capacitance . . . . . . . . 1160 ~ 1510 pF
Crss Reverse transfer capacitance . . 29 ~ 38 pF

The thermal issues limit 400V*60A with an infinite heat sink @ 25'C and a single 10us pulse. This raises the chip to the maximum temperature and fusing current limit. The cooling time depends on the mass of your "finite" heatsink. Given that they test this with a 1 shot or special heavy baseplates and Peltier-controlled temperatures at some low duty-cycle, you can understand this FET won't work for your application.

You must consider the mass of the chip only for a single 10 us thermal time constant of the junction. but you must consider the hundreds of ms or many seconds for your fan-free heatsink to get a thermal decay time constant. (Use Thermodynamic theory)

This chip is similar to a 1x1 cm FPGA which has a similar array pad design and you can expect a thermal resistance, Rca on the order of 10 to 30 °C/W or 20 to 60 times your junction to case Rjc.

The total temp rise is average power (Pavg) * Rcase-ambient (Rca)* duty cycle * (Rjc + Rca) = Trise above ambient.

This can be 150 to 200 °C or more for a few solder liquidus seconds during reflow soldering but no more. Ramp rate is also critical. But a good design will only be 85 °C for high reliability to prevent thermal runaway.

You need some FET massive that can be clamped to a large insulated heatsink! Or change the design to a saturated hockey puck-sized BJT or brick-IGBT instead of 70V across the switch.

When they specify the case is limited 300W @ 25°C as the maximum case power, that's with an infinite heatsink ( or maybe a water-cooled Alum-clad substrate) So you can kiss your duty factor goodbye to;

d.f = 300W / (Tc= 85°C-Tamb=?) * (Rjc+Rca) / Ppk

e.g. 300W / 40°C (= 85-35ambient) * 20°C/W (= 150) / 28000W x100% = 0.5% duty factor.


Look up Mitsubishi 6th generation IGBTs (brick) .

Look up Arrhenius Effect. MTBF reduces 50% for approx. every 10°C rise in the junction above room temp.

Write better (realistic) design specs.


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