Let's consider the three phase multilevel NPC inverter shown below.
Let's focus on the first phase leg in the occasion when we want to get v1 = Vdc/2 as output phase voltage, as shown in the picture below (this is the same as asking that in the circuit above the voltage between phase A and the Z point is 0).
Lets's also suppose phase current is positive so it's going towards the load and away from the DC bus.
Every textbook I found says that in this case the current would be flowing through the higher clamping diode and the S2 switch.
It seems to me that if we assume this is the current path than the antiparallel diode of S4 is reverse biased so it can't conduct.
But if one didn't know this is the current path, how could it be possible to demonstrate that the antiparallel diode of S4 is reverse biased, thus closing the alternative path for the output current through the antiparallel diodes of S3 and S4?
Sorry if this is a really simple question but I couldn't find the answer anywhere.