Why does the counter output remain unknown (x)? I expect the counter to increment.

module Seven_seg(SW, CLK, SSEG_CA, SSEG_AN, LED);

    input [3:0] SW;
    input CLK;
    output reg [7:0] SSEG_CA;
    output reg [7:0] SSEG_AN;
    output reg [3:0] LED;

    slow_clock S1 (CLK, Clk_Slow);          //initializes clock
    initial begin
        SSEG_AN <= 8'b11111110;             //start at first anode
    always @ (posedge Clk_Slow)
        case (SW)
            4'b0000: SSEG_CA <= 8'b11000000;
            4'b0001: SSEG_CA <= 8'b11111001;
            4'b0010: SSEG_CA <= 8'b10100100;
            4'b0011: SSEG_CA <= 8'b10110000;
            4'b0100: SSEG_CA <= 8'b10011001;
            4'b0101: SSEG_CA <= 8'b10010010;
            4'b0110: SSEG_CA <= 8'b10000010;
            4'b0111: SSEG_CA <= 8'b11011000;
            4'b1000: SSEG_CA <= 8'b10000000;
            4'b1010: SSEG_CA <= 8'b10001000;
            4'b1011: SSEG_CA <= 8'b10000011;
            4'b1100: SSEG_CA <= 8'b11000110;
            4'b1101: SSEG_CA <= 8'b10100001;
            4'b1110: SSEG_CA <= 8'b10000110;
            4'b1111: SSEG_CA <= 8'b10001110;

    LED <= SW;

        case (SSEG_AN)
            8'b11111110: SSEG_AN <= 8'b11111101;
            8'b11111101: SSEG_AN <= 8'b11111011;
            8'b11111011: SSEG_AN <= 8'b11110111;
            8'b11110111: SSEG_AN <= 8'b11101111;
            8'b11101111: SSEG_AN <= 8'b11011111;
            8'b11011111: SSEG_AN <= 8'b10111111;
            8'b10111111: SSEG_AN <= 8'b01111111;    
            8'b01111111: SSEG_AN <= 8'b11111110;

module slow_clock(CLK, Clk_Slow);
    input CLK;
    output Clk_Slow;

    reg [31:0] counter_out;
    reg Clk_Slow; 

initial begin 

//this always block runs on the fast 100MHz clock

    always @(posedge CLK) begin 
   counter_out<=counter_out + 32'h00000001; 
   if (counter_out>32'h00F5E100) begin 

enter image description here

//test bench

module Seven_seg_tb();
    reg [3:0] SW;
    reg CLK;
    wire [7:0] SSEG_CA;
    wire [7:0] SSEG_AN;
    wire [3:0] LED;
    Seven_seg uut(SW, CLK, SSEG_CA, SSEG_AN, LED);

    initial begin
        SW = 4'b1111;
        CLK = 1;

        #5 CLK = ~CLK;

    always @ (posedge CLK)begin
        SW = 4'b0000;
        SW = 4'b0001;
        SW = 4'b0010;
        SW = 4'b0011;
        SW = 4'b0100;
        SW = 4'b0101;
        SW = 4'b0110;
        SW = 4'b0111;
        SW = 4'b1000;
        SW = 4'b1010;
        SW = 4'b1011;
        SW = 4'b1100;
        SW = 4'b1101;
        SW = 4'b1110;
        SW = 4'b1111;
  • \$\begingroup\$ You need a reset. \$\endgroup\$
    – Voltage Spike
    Dec 2, 2022 at 19:19
  • \$\begingroup\$ @VoltageSpike: My answer says a reset would solve the problem. Also, I voted to reopen since the question was edited to add sufficient detail that was originally lacking. Could you do the honors so others can add answers as well? \$\endgroup\$
    – toolic
    Dec 2, 2022 at 19:36

1 Answer 1


This is a subtle simulation problem. You have a simulation race condition at time 0.

The CLK signal is declared as a reg which means it is initialized as x (unknown at time 0). Also at time 0, you set CLK to 1. This x->1 transition is treated as a posedge. This triggers the always block in the slow_clock module.

At time 0, counter_out is also initialized to x, and it essentially stays at x for the remainder of the simulation. The counter_out<=32'h00000000; assignment in the initial block (also at time 0) does not take effect.

A quick way to fix this is to change this line in the testbench:

    CLK = 1;


    CLK = 0;

That delays the posedge to a time after 0, allowing the counter to be initialized to 0.

A better way to solve it would be to add an asynchronous reset input signal to the design and reset the counter to 0 that way.

Also, since the clock divide ratio is really big, you need to let the simulation run for more that 16 million CLK cycles to see the design outputs change from x to known values.

enter image description here


Not the answer you're looking for? Browse other questions tagged or ask your own question.