I want to create complementary PWM with a dead time to drive 2 MOSFETs at a time. But I think in LTSpice deadtime is something difficult.

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    \$\begingroup\$ If you use PWL you can enter pairs of (time, voltage) and customize your waveform with any sort of timing you want. \$\endgroup\$
    – chamod
    Commented Dec 2, 2022 at 1:11
  • 1
    \$\begingroup\$ in ltspice you can make dead time using and and gate and a delay line, \$\endgroup\$ Commented Dec 2, 2022 at 3:17

2 Answers 2


You can use the PULSE waveform by adjusting the delay parameter and on time.

The PULSE waveform has these parameters: Vinitial, Von, Tdelay, Trise, Tfall, Ton and Tperiod. Both the high and low-side signals will have the same values for these parameters: Vinitial, Von, Tperiod, Trise and Tfall.

For example, for a 5V 100 kHz pulse train we could have:

Vinitial = 0, Von = 5, Tperiod = 100u, Trise = 1u, Tfall = 1u

and the difference in the high- and low-side signals will only be in Tdelay and Ton.

Let's say we want a dead time of 5u before and after each edge. Then each signal will be on for only 40u instead of 50u.

So the signal which initially starts at 0V can be specified with:

Tdelay = 55u, Ton = 40u

and the one that initially starts high with:

Tdelay = 5u, Ton = 40u

Here is what the signals look like. The traces are:

green - unmodified pulse, blue - signal that starts high, red - signal that starts low

enter image description here

In the general case where you have a pulse which is high for \$\tau_H\$ and low for \$\tau_L\$ (without dead time) and you want a dead time of \$\tau_D\$ between transitions, use the following settings for Tdelay and Ton:

Signal 1: Tperiod = \$\tau_H+\tau_L\$, Tdelay = \$\tau_D\$, Ton = \$\tau_H-2\tau_D\$

Signal 2: Tperiod = \$\tau_H+\tau_L\$, Tdelay = \$\tau_H-2\tau_D\$, Ton = \$\tau_L-2\tau_D\$

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    \$\begingroup\$ I find it easier to make a pulse that starts low by using PULSE(5 0 5u 1u 1u 40u 100u). That way your delay is exclusively the dead time, not the dead time plus a number that needs to be changed whenever you change frequencies of operation. There's no rule saying the "on" voltage has to be higher than the initial voltage. \$\endgroup\$
    – Hearth
    Commented Dec 2, 2022 at 15:46
  • \$\begingroup\$ @Hearth have you tried your suggestion? It did not give me a correct result when I tried it. In fact, neither did the equations posted by ErikR work. To make this work and make it adjustable, I made a parameter .param tdead=5u and then defined both signals as PULSE(0 10 {tdead} 70n 70n {20u-tdead} 40u) and PULSE(0 10 {20u+tdead} 70n 70n {20u-tdead} 40u). I have no idea where I made a mistake, but if someone does the same mistake I hope this helps them \$\endgroup\$
    – Anas Malas
    Commented Jan 21, 2023 at 15:10
  • \$\begingroup\$ @AnasMalas The exact syntax may be slightly wrong, I was doing that from memory. I've used this general method before, though. \$\endgroup\$
    – Hearth
    Commented Jan 21, 2023 at 15:49
  • \$\begingroup\$ Ah I can no longer edit my comment. I added one more parameter (press "s" then paste then, place it anywhere on the schematic): .param ton=38u. Use these expressions for the sources: PULSE(0 10 {tdead} 70n 70n {ton-tdead} 40u) and PULSE(0 10 {ton+tdead} 70n 70n {40u-ton-tdead} 40u) where the 40u is just the period \$\endgroup\$
    – Anas Malas
    Commented Jan 21, 2023 at 16:07

You can implement a deadtime quite simply actually by associating a few gates together with two \$RC\$ networks as shown below:

enter image description here

The wanted deadtime is a delay parameter and the two resistors and can be conveniently parametrized. Here, we have 150 ns as shown in the resulting waveforms. It is assumed that the gates deliver 5 V and toggle at a 2.5-V transition level without significant hysteresis.

In an integrated circuit, these dead-times are quite common and designers generate them with a delay brought by several cascaded logic gates as in the below circuit. In the example, the buffer provides the accumulated delay which is also easily adjusted. If LTspice provides these digital gates, it is easy to build:

enter image description here

And there you go with the LTspice version:

enter image description here

Once the digital symbols for the buffer and AND gates are placed on the schematic, right-click on the symbol and add the parameters statements in the SpiceLine to set the high level to 5 V, low to 0 V and the toggling level at 2.5 V - which is, by default \$\frac{V_H+V_L}{2}\$ so ref can probably be ignored.

The cool thing here is that you can add this circuit to more complicated switching converters like those built around half- or full-bridge and add dead-time to any PWM outputs.

  • \$\begingroup\$ Verbal Kint, which simulation program are you using? \$\endgroup\$
    – user327367
    Commented Dec 2, 2022 at 7:03
  • \$\begingroup\$ @Oguzhan, in this particular example, this is SIMetrix/SIMPLIS and this simple arrangement will work well on their free demo version Elements. \$\endgroup\$ Commented Dec 2, 2022 at 7:55
  • \$\begingroup\$ @VerbalKint There may be a way to simplify all that. ;-) \$\endgroup\$ Commented Dec 3, 2022 at 8:30
  • \$\begingroup\$ @aconcernedcitizen, you are the expert in LTspice : ) Your solutions is even simpler and saves passive elements: it's a good alternative, I agree! \$\endgroup\$ Commented Dec 3, 2022 at 15:19
  • \$\begingroup\$ @VerbalKint Well, confetti's on me for the promotion! The champagne is on you... \$\endgroup\$ Commented Dec 3, 2022 at 17:42

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