Designing a jk flip-flop that has a toggle state when j=k=0

Question

Can we design a JK flip-flop using only NOR gates? The logic circuit implementation would look like this.

In this case the toggle state would be when j=k=0 instead of when they're equal to 1.

Answer 1

Despite circuits resembling yours being ubiquitous in the internet, the circuit actually has serious problems is unreliable. (An example of the broken NAND version, for example can be found at this site

The basic problem with your circuit, and the NAND version is that it is a latch with feedback, and neither a master-slave flip-flop, nor an edge triggered flip-flop. As a result, when feedback is enabled by setting the J and K inputs appropriately, it is not guaranteed that that the circuit won't oscillate during a clock pulse, nor is it guaranteed that the circuit will actually change state.

Here is an implementation of your circuit in CircuitLab

^{simulate this circuit – Schematic created using CircuitLab}

As you can see, it oscillates, rather than toggles on clock pulses.

To see toggle flip-flops that actually work, see this question and its answers. If you swapped the nand gates for nor gates in either a Master-Slave JK flip-flop, or a true edge triggered flip-flop, you will, if you do it right, get a genuine flip-flop that toggles when J=K=0.