# Is the invalid state of an SR latch also undefined?

I understand that if both the Set and Reset inputs of an SR latch are high, the output of both Q and Not-Q is low and this is considered an invalid state.

But in this situation is the output also undefined? Or is it a reliable outcome? For example, if the two outputs of this latch were input into a NOR gate, could I reasonably expect that the NOR gate output would go high whenever the S and R inputs both are high?

The other answers are correct. The so-called "invalid state" of a SR latch is well defined, and can be used. However, there is a transition that is problematic. If both set and reset are active, and then both inputs become inactive very close together timewise, the latch may enter a metastable state. This doesn't always happen, but in a circuit with possibly millions of transitions per second, metastable states can be a serious concern. AFAIK, the danger of metastable states can be mitigated, by making the mean time between failures sufficiently long, but the danger cannot eliminated completely if the inputs to the latch may change completely independently of each other, and possibly simultaneously.

There are multiple issues associated with metastable states. One of these is that if there is more than one device reading a metastable output, the different devices may read different values, and this may lead to a corruption and failure far beyond that of the original latch.

If the latch is constructed as a common cross-coupled NOR latch then setting both inputs high will cause both outputs to go low. This is generally considered to be invalid but it is not an undefined state.

If you connect a NOR gate to the two outputs then the output of the NOR gate will be high when both S and R are high.

• So it's called invalid not because you can't use it, but because Q and not-Q aren't supposed to be the same? Commented Dec 3, 2022 at 15:20
• That's correct. Also, if you try to go from S=R=1 directly to the hold state (S=R=0) then the outputs will be undefined. Commented Dec 3, 2022 at 16:15

So it's called invalid not because you can't use it, but because Q and not-Q aren't supposed to be the same?

Correct. AND - you can use it.

For the classic dual-NAND-gate SR, If you hold one input low and toggle the other one, one of the outputs also will toggle. If you hold S low and toggle R, the Q output will stay high while the -Q output is the inverse of the R input. Strange way to make an inverter, but there it is.

Look at the datasheets for the CD4044 quad NAND SR flipflop. If you hold the R input low and toggle the S input, the output is frozen low no matter what the state of the S input. But if you hold the S input low and toggle the R input, the output will toggle in phase, making the circuit an overly-complex non-inverting buffer.

If 4044 the internal circuit were just slightly different, it would mimic 2-gate circuit operation and you could use a section as an inverter in a pinch. Way more useful that a low-power buffer IMHO. Back in the 70's I pointed this out to one of the original 4044 designers, and he said I was not the first person to point this out. IOW I think he was tired of hearing about it.