enter image description here

Circuit explanation:

I'm trying to make a circuit which turns button pushes into binary data. The button push slowly discharges a capacitor which then triggers a 555 monostable stable circuit to prevent bouncing. The output of the monostable circuit is then sent into Data_in of the shift register (74HC595). The Register_clock triggers on every falling edge and latches in data that is in the shift_register, which latches in data on the inverse of the register_clock.

Problem: The shift register outputs arbitrary data. It almost appears like the input is floating.

Here is a reddit post demonstrating the current circuit's behaviour.( after swapping out for a 74hc04) https://www.reddit.com/r/beneater/comments/zev60t/does_anyone_know_the_cause_or_fix_for_this_issue/?utm_source=share&utm_medium=web2x&context=3

  • \$\begingroup\$ Thank you for the descriptopn and schematic. That's a great start! Please draw your schematics with main signal flow from left to right, it makes it much easier to read (and rotating the image so we don't have to rotate out screens helps a lot too ;) ) \$\endgroup\$
    – kruemi
    Dec 5, 2022 at 7:44
  • \$\begingroup\$ Do you have a multimeter? If you measure the voltage at the switch, over the 1k resistor, it would confirm the floating voltage. \$\endgroup\$
    – Justme
    Dec 5, 2022 at 7:55
  • 7
    \$\begingroup\$ Don't forget "decoupling" capacitors on every digital IC ... \$\endgroup\$
    – Antonio51
    Dec 5, 2022 at 8:22
  • 6
    \$\begingroup\$ Don't mix technologies (CMOS & TTL) unless necessary. Many seem to be compatible, but there are subtle issues that can cause headaches. 74AC14 parts are readily available. \$\endgroup\$
    – Mattman944
    Dec 5, 2022 at 8:44
  • 3
    \$\begingroup\$ Schematics are much easier to read if you don't try to draw them using the physical layout of the ICs. For example, there no reason to draw a block of 6 x inverters all in one place like that when the individual logic elements are used in different places in the circuit. A schematic is not a PCB layout. \$\endgroup\$
    – brhans
    Dec 5, 2022 at 14:32

5 Answers 5


If your LED connected to the 555 output is illuminating correctly, then the main thing I can see that looks wrong is that your clock inputs and 'data in' on the 74HC595 need swapping over.

As it is wired currently, the data in is debounced, but the clock input isn't, so every button press could clock in several bits. Swapping those inputs will give a clean clock pulse that will clock the correct data in.

  • \$\begingroup\$ Hello, Thank you for your response. I do see that my clock input is bouncing, but this should not contribute to how my shift register is latching in arbitrary data, or does it? If so, please enlighten me. Also, what do you mean by "swapping the inputs"? I get the general gist of your comment but not the details. \$\endgroup\$ Dec 6, 2022 at 8:47
  • \$\begingroup\$ Your clock input needs to be debounced, your data input may not require the debouncing circuitry. You could literally try swapping the connections for those pins on the 74595 to swap your debouncing circuitry to the clock input (I haven’t spent much time looking in detail). It is likely that you have the issues described in the other answer, but multiple clock pulses will cause problems. \$\endgroup\$
    – HandyHowie
    Dec 6, 2022 at 19:54
  • \$\begingroup\$ Your switch upon reflection does not need to be debounced for SI but does need to be debounced for the delayed clock. As I defined as a spec in my answer. You mustuse a clock window filter to allow only between > 20ms and less than x say >=150 ms. . Thus swap SI and SLK . This will work, SVP and switch to SI, ASAP. Then RLK must occur at least 1 us after SCK so add RC to RCLK as I answered. \$\endgroup\$ Dec 11, 2022 at 17:45
  • \$\begingroup\$ Good thinkin' Howie \$\endgroup\$ Dec 11, 2022 at 17:48

Likely multiple reasons.

The 595 is a HC type, and the 04 is an LS type.

The output of LS type chip is incompatible with input of HC type.

The pushbutton circuit is also a problem. First of all it too is not compatible with LS type input, and it has no debouncing.

Easiest fix would be to use a HC04.

For an LS04, the 1k pull-down is too weak. Which is why generally LS type inputs have a pull-up and the pushbutton would just ground the input.

Also to make LS output compatible with HC input, you would put a pull-up resistor to make sure the output high voltage is within HC input limits.

  • \$\begingroup\$ Hi, Thank you for your reply. I just tested with the 74HC04, and now, all the inputs stay off no matter what. Just for curiosity, how exactly are the two chip types not compatible? \$\endgroup\$ Dec 6, 2022 at 9:10
  • 2
    \$\begingroup\$ @Turtleishly It is explained in all basic logic compatibility documents. The LS output high voltage is not enough to what the HC input voltage requirement is. Officially it is not guaranteed to work. \$\endgroup\$
    – Justme
    Dec 6, 2022 at 9:15

To put a few numbers on @Justme's answer I found a datasheet for each chip: 74HC595 74LS04.

Here we can see that the HC595 can operate at 2-6V supply, and lists its input specifications at 4.5V supply (they will be slightly higher at 5V supply).

  • High-level input voltage (V_IH) = 3.15V (min)
  • Low-level input voltage (V_IL) = 1.35V (max)

This means that inputs from 0-1.35V are registered as low, 1.35-3.15V as indeterminate (may be low, may be high - no guarantees given), and 3.15-4.5V as high. Again note that these all shift slightly up when supply goes from 4.5V to 5V.

On the other hand, the LS04 requires supply between 4.5V and 5.5V, and lists its specs at 5V supply:

  • V_OH = 2,7V (min), 3,4V (typ)
  • V_OL = 0,4V (max)

As you can see, the low value is golden - 0,4V max out compared to 1.35V min in.

But the high is a problem: A minimum of 3.15V is required, but the output only promises 2.7V - even if it claims that 3.4V is typical. And this is before we account for the 4.5V <-> 5V supply difference.

The HC595 also list V_IH at 2V and 6V as 1.5V and 4.2V min. If we look at ratios to do a bit of extrapolating, then this happens:

  • 1.5/2 = 0,75
  • 1.35/4.5 = 0.7
  • 4.2/6 = 0.7

This suggests that at 5V supply the min V_IH is at 5V * 0.7 = 3.5V, which is higher than even the typical V_OH of the LS04. Of course, this is only a guess but it does paint a grim picture.


Why is my shift register latching in garbage data?

Answer: Garbage In ... Garbage out

It seems to me you want to make a better switch debounce circuit. Although you could make it a Morse Code binary display on "Dah's" and "Dit's by using the switch duration trailing edge to decode the duration of the switch after it is debounced for 10 ms. Then yank HC04, Q1 and 555.

Let's define the "Dah" as > 150 ms and "Dit" as < 150 or make it X with a single R to control the Morse Code delay threshold..

To debounce to ~20 ms with a button switch bounce time of 5ms use 22 nF and 1Meg or 2.2 nF//10Meg pulldown.

Then use a LPF to define the delay of CLK relative to debounced D. Let LPF RC=T=150 ms then with 50% threshold +/-33% the delay will be roughly 150 ms on the training edge of the buffered inverted switch = CLK . Meaning a short "Dit" CLK's a 0 and a long Dah clocks a 1. Now your binary shift register will display your Morse Code at any repetition rate but active Pulse width modulated when pressed on trailing edge.

Now you use the debounced switch for SI (data) and the decoded delay

I don't know how you can use a switch to clock events with a shift register that is not a counter other than like Morse Code Events. But the leading edge must be filtered to 10ms Thus a "Dit" event is a time window comparator between 10 ms and 150 ms clocked event and anything longer is a "Dah". But this does not decode the Morse Code into characters or counter characters. That's something else.

YOur choice is to define if a Dah = 0 or 1. I would choose 0 as it takes longer to say like Dah.

The SCK or shift clock is your decoded switch delay output rising clock and RCK is the register latch which is just any delay of say > 1 us after rising edge of SCK but < 10 ms. So in total you need 4 caps for charge storage

  1. Vdd denoise < 1us
  2. Switch denoise < 10ms
  3. Morse dah/dit decode > 150 ms
  4. RCLK Register latch CLocK


simulate this circuit – Schematic created using CircuitLab

In the meantime, I'll send you a pattern to use.

• • • – – – • • •


  • ways to send secret messages, check out these eBooks on Hoopla: Codes by Kjartan Poskitt and Codes, Ciphers and Secret Writing by Martin Gardner

enter image description here

A picture is worth a thousand words.

The experts might notice a POR (reset) added RC circuit or if you did, bravo.

  • \$\begingroup\$ Sorry I did not bother to explain why you are getting noise on your bandaids. If you had a design spec with a timing diagram, I would have. \$\endgroup\$ Dec 10, 2022 at 13:36
  • \$\begingroup\$ The OP MAY not inderstand the term "bandaid" even thoughit will be fmiliar to many. I noted much the same in a comment as "The series of inversions, emitter follower transistor, interesting RC delay at top right and two monostables lead to an apparently chaotic system. " I'm not certain what they expect switch timing to achieve. I asked re that in a comment. \$\endgroup\$
    – Russell McMahon
    Dec 12, 2022 at 10:01
  • \$\begingroup\$ Bandaids protect a design injured by lack of experience. The timing is clear to me and well-defined in my answer. Also Murphy's Law ( if anything can be reversed...) i.stack.imgur.com/RMpd3.png (not clear enuf?) \$\endgroup\$ Dec 12, 2022 at 10:07
  • \$\begingroup\$ 1. I was not complaining per se :-) 2. Yes - I and you know what bandaids are. The OP may. 3. What I'm not sure of re timing is what the OP expects re data and clock when they press and release the button. Their willingness to add a monostable in the 2nd circuit without explict discussion of delay compared to the first monostable suggested to me (perhaps wrongly) that timing issues are not clear to them. \$\endgroup\$
    – Russell McMahon
    Dec 12, 2022 at 10:13

Your shift-register clock is driven directly by your pushbutton, with no debouncing. The register may be clocking multiple cycles at a single push.

Use of a gate-pair from a 74C14 in the SR clock path (or other Schmitt triggered gate with hysteresis) may solve your problem.

enter image description here

  • \$\begingroup\$ I implemented it. I ran my button through another separate 555 debouncing circuit and into the shift register. nothing changed. Now My shift register latches in data, but unreliably. And very inconsistently. \$\endgroup\$ Dec 9, 2022 at 7:49
  • \$\begingroup\$ @Turtleishly What data do you intend to be latching in? || As clock and data are fed from the same source - the pushbutton - with data on the delayed rising edge and clock on the (differently delayed + button hold time) falling edge edge you should get results based on the semi random relationship of the two timing streams. I see so far no reason to think that it is not doing what it should (!). || It would be a REALLY good idea if in your question you described what you think should happen and why. ... \$\endgroup\$
    – Russell McMahon
    Dec 9, 2022 at 10:37
  • 1
    \$\begingroup\$ @Turtleishly ... The series of inversions, emitter follower transistor, interesting RC delay at top right and two monostables lead to an apparently chaotic system. \$\endgroup\$
    – Russell McMahon
    Dec 9, 2022 at 10:37

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge that you have read and understand our privacy policy and code of conduct.

Not the answer you're looking for? Browse other questions tagged or ask your own question.