DDR3 and DDR4 memory routing can be confusing to for length matching because of the many tolerances and specs of all the different busses.
How do I length match different signal classes for DDR3 or DDR4 routing on a PCB?
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The best way I have found is to first route the CK (clock or main clock) and this should be the longest trace. The command address and control signals should be less than the main CK signal (so that the data or address signals arrive before the clock). The command, address an control signals should all be matched, but usually the matching can be better than the manufacturers recommended delay or lengths.
The data signals should be matched by group and typically have a much higher tolerance because they have read and write delay registers that are set with training the memory.
This scheme works for both DDR3 and DDR4 (and possibly higher specs). This picture sums it up.