I have some questions these are I am not sure:
I have designed a board that has classical 2 side PCB design. Frequency is not a big issue for me but with ESD my CPU resets itself. (CPU clock 20 Mhz, and some data transfer lines at 10 Mhz, 2Mhz, 400 Khz)
How does returning current work for two-sided PCB? Everything is ok for 4-layer PCB with a solid GND or Pwr, but how can I design it for a two-sided PCB to avoid forming EMI from returning currents?
If I use 0603 smd decoupling capacitors instead of 0805 smd decoupling capacitors does it make any difference?
I couldn't understand something with this picture for returning currents. This is Signal/Pwr-Gnd/Pwr-Gnd/Signal Design. The point that I couldn't understand what does it mean to say “Return current on top surface of layer” or “Return current on bottom surface layer”. Isn't that the same place, surface of full of GND?
In fact, I couldn't understand layer2 and layer3. Which surface has full of Gnd or Pwr/Gnd? (sorry for this easy question.) And how does current go from layer2 bottom surface to layer2 top surface? I can see that current goes from Layer3 to Layer2 by via. But how does it travel between the surfacs?
My PCB is complex for one side design. I have to use side 2 too, so that I can't allocate one side for solid ground. I want to learn about these returning currents. I have some Data traces that will handle transfers at 16 Mhz. How can I design returning paths for these? Do I have to worry about them? What is the perfect design for my two sided board for these returning currents? As I said, I can't allocate all of side for ground. And what is the perfect design for my GND and VCC? Huge pieces of GND under high speed data traces or just traces of GND? In fact, I am not sure how to design Vcc and GND for the best.
This is my PCB layout. I think it has design mistakes in it. What are these, in your opinion? Red one is Top Layer, Blue one is Bottom.
I have censored some of parts with yellow. So dont worry about them. Thanks for help.