# Returning Currents for two side boards and returning current questions

I have some questions these are I am not sure:

I have designed a board that has classical 2 side PCB design. Frequency is not a big issue for me but with ESD my CPU resets itself. (CPU clock 20 Mhz, and some data transfer lines at 10 Mhz, 2Mhz, 400 Khz)

1. How does returning current work for two-sided PCB? Everything is ok for 4-layer PCB with a solid GND or Pwr, but how can I design it for a two-sided PCB to avoid forming EMI from returning currents?

2. If I use 0603 smd decoupling capacitors instead of 0805 smd decoupling capacitors does it make any difference?

3. I couldn't understand something with this picture for returning currents. This is Signal/Pwr-Gnd/Pwr-Gnd/Signal Design. The point that I couldn't understand what does it mean to say “Return current on top surface of layer” or “Return current on bottom surface layer”. Isn't that the same place, surface of full of GND?

In fact, I couldn't understand layer2 and layer3. Which surface has full of Gnd or Pwr/Gnd? (sorry for this easy question.) And how does current go from layer2 bottom surface to layer2 top surface? I can see that current goes from Layer3 to Layer2 by via. But how does it travel between the surfacs?

Edit 1

My PCB is complex for one side design. I have to use side 2 too, so that I can't allocate one side for solid ground. I want to learn about these returning currents. I have some Data traces that will handle transfers at 16 Mhz. How can I design returning paths for these? Do I have to worry about them? What is the perfect design for my two sided board for these returning currents? As I said, I can't allocate all of side for ground. And what is the perfect design for my GND and VCC? Huge pieces of GND under high speed data traces or just traces of GND? In fact, I am not sure how to design Vcc and GND for the best.

Edit 2

This is my PCB layout. I think it has design mistakes in it. What are these, in your opinion? Red one is Top Layer, Blue one is Bottom.

I have censored some of parts with yellow. So dont worry about them. Thanks for help.

• Hi, welcome to Electrical Engineering! Please do not ask multiple questions in one question, instead just add multiple questions using the "Ask question" button in the top right.
– user17592
Commented Apr 5, 2013 at 15:00
• if your CPU is resetting with ESD, look closely at the location of your capacitor on the reset line. You should place this capacitor as close to the CPU as possible. And if you do not have a capacitor on the reset line add it Commented Apr 5, 2013 at 15:18
• Please be clearer with your questions. Commented Apr 12, 2013 at 12:43
• Could you please share where you have obtained the picture with the return currents, looks interesting.
– user94729
Commented Apr 23, 2018 at 11:40

1.- Grounding for 2 layer PCB is a really difficult point. If you cann't use Bottom layer for a GND plane, you have to use a ground grids. With this technique you want to create a grid of ground in bottom layer. It will work like a ground plane. It's a difficult technique to explain in this post.

2- It depends but it's probably that 0603 capacitor have a lower ESR and a lower ESL.

3- You have to consider the "skin effect" for high frequency. At these frequency current flows only on the surface of the conductor. It's for that reason that you can consider the "botton side (ot the top side) of the third layer" o the "top side (or bottom side) of the second layer". It's a messy way to speak.

Regarding the image you refer. Probably second layer is ground and third layer is a Power, but we don't know. We know that they are planes and the return current flows in nearest plane, regarless it's a ground o power.

If you prefer you can symplify the image with this:

return current on top surface of layer 2 = return current on layer 2 return current on bottom surface of layer 3 = return current on layer 3

What i say next doesn't consider such phenomena as a plane copper PCB layer transmitting RF aka it being a patch antenna. That's another story...

Make your 2 layer board with a ground plane connected to 0V on the non-component side. It will dramatically reduce problems with chips resetting because the CPU's reset capacitor (assuming you have one) will be firmly held at the same 0V potential is your CPU (example). ESD may not produce large currents but it can generate "ground" voltages on tracks that are several hundred millivolts. This is due to the track having inductance. A ground plane is the lowest resistance and lowest inductance 0V you can produce on a circuit board.

0603 versus 0805 won't be an issue on your design but it can be an issue on very high frequency RF circuits. A bigger cap will have more self-inductance for instance.

The returning signal current will always exploit the lowest inductance/resistance path that is available to it and that means it mirrors the forward signal current in the ground plane thus the inductance loop of forward and return currents is minimal - inductance is all about shape and area - the smaller the area the lower the inductance.

• @user22165 I think if you can post a circuit diagram we might be able to help you more. Having tracks on the ground plane side is not ideal but neither is it a rule that cannot be broken but, care needs to be taken and it's impossible to give pointers without generalizing every sort of scenario so, a circuit will help a lot. Commented Apr 7, 2013 at 9:06
• Ok i will add one that i have faced with EMI problems. So you can give some helpfull advice about it. Thanks to you. Commented Apr 7, 2013 at 10:19
• I have added my PCB design. Commented Apr 8, 2013 at 6:46
• @user22165 It was the circuit diagram I wanted to see however, I can see this is a complex design and it immediately struck me that this should be a 4-layer PCB with a good solid ground-plane on one of the middle layers. If you still want to pursue a 2-layer board that's OK but you may never get the ESD/RFI/EMC performance you need. I wanted to advise about the circuits themselves but the layouts have told me a fair amount. Commented Apr 8, 2013 at 8:56