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Typically microcontrollers use an input clock source with a certain frequency. This clock source is then divided and multiplied to a PLL frequency which is much higher. Finally, the PLL frequency is divided again to get the target peripheral frequency.

For example here are several ways to get the target 48 MHz frequency from a 16 MHz clock source:

PLL = 16MHz / 1 * 12.0 = 192.0MHz, PLL / 4 = 48.0MHz
PLL = 16MHz / 1 * 15.0 = 240.0MHz, PLL / 5 = 48.0MHz
PLL = 16MHz / 2 * 18.0 = 144.0MHz, PLL / 3 = 48.0MHz
PLL = 16MHz / 2 * 24.0 = 192.0MHz, PLL / 4 = 48.0MHz
PLL = 16MHz / 2 * 30.0 = 240.0MHz, PLL / 5 = 48.0MHz
PLL = 16MHz / 3 * 27.0 = 144.0MHz, PLL / 3 = 48.0MHz

As you can see, there are several different PLL frequencies that are possible, while still producing the same end result.

Is one of these better that the other? Should I keep dividers and multipliers as big or small as possible? Should the PLL frequency be as big or small as possible?

MCU manuals don't typically give much advice, other than give minimum and maximum values for all parameters. It seems that other than those, anything goes.

Clarification: Apparently there are external PLLs, but this question is about MCUs where PLL circuit is internal, and multiplier and divider values have to be chosen from set provided in MCU registers at startup. This is how I have seen it being done in ARM Cortex-M cores.

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  • \$\begingroup\$ Does the MCU require you to add an external filter for the PLL? If so then start from there. \$\endgroup\$
    – Lundin
    Dec 8, 2022 at 9:31
  • \$\begingroup\$ @Lundin As far as I understand, PLL has always been internal part MCUs I've worked with (ARM Cortex-M cores); so I have not heard of external filters for PLL? (I am not actual hardware designer myself, so perhaps I am misunderstanding something) Unless filter you are referring is part of external crystal resonator circuit? \$\endgroup\$
    – user694733
    Dec 8, 2022 at 10:12
  • \$\begingroup\$ Some MCUs require an external loop filter made of passives like in this schematic to be added externally. Attuned to desired frequency, accuracy and locking speed, as per some manufacturer requirements. I haven't seen this on Cortex M either, but then on the parts I usually work with, I just go with some default oscillator config like 48MHz + external quartz and no PLL tweaking. \$\endgroup\$
    – Lundin
    Dec 8, 2022 at 10:21
  • \$\begingroup\$ Choose always the "frequency" ... that does not impact EMI to the neighborhood ... \$\endgroup\$
    – Antonio51
    Dec 8, 2022 at 12:21
  • \$\begingroup\$ Yes, there usually are optimal values, but it might depend on what you want to optimize - jitter, power consumptiom, etc? If you have a specific MCU then mention it, there likely is an optimal value from manufacturer. It might not be in data sheet, but somewhere else. \$\endgroup\$
    – Justme
    Dec 8, 2022 at 15:31

3 Answers 3

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There are multiple considerations that determine what is optimal:

For the most part, a higher divider just makes your feedback path slower, so locking takes longer.

An even-numbered divider has the advantage that it ignores falling edges on the input clock, so that is a big plus if the duty cycle isn't exactly 50% (and for external clocks, that can happen easily).

If you cascade PLLs you want to ensure they have different loop bandwidth.

If you want to generate multiple output clocks, choose a loop frequency that is a multiple of all of them if possible.

For example, if you also need a 10 or 20 MHz clock for an SPI bus or a timer, and the input clock is from an external crystal, the "divide by two, multiply by thirty" configuration is likely best.

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Assuming internal filter. The PLL only updates on each incoming clock cycle from the output of the pre-divider, so the lowest jitter will usually be with the lowest pre-divider value.

If you don't care about jitter, it doesn't matter. If you use the clock for USB it may be important, so in this case I'd use settings #1 or #2. Then I'd put the VCO in the middle of its range, so that would be #1.

However there may be other factors: for example if you want to scale down the clock to save power (or for other reasons) without having to re-lock the PLL, then you'll have to run the VCO at a constant frequency and only change the output divider. That could force you to choose a specific VCO frequency.

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If we assume that, for your particular application, the 48MHz signal has to be generated externally, then I would design the simplest possible circuit. This is your first option. No initial division. *12 then simple binary division by 4 is easier than any other.
In all matters of electronic design the rule should be "keep it simple" unless there is an overwhelming reason to do otherwise.

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