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I am trying to get needed clearance to pads that are in a net by using net classes, and the design rules work with traces, but not the pads during poly pour. How is this easily done using net classes in the schematic editor? The design rule based on net class test doesn't seem to extend to pins/pads.

Example (In PCB Rules and Constraints Editor Clearance rule):

First Object: InNetClass('Primary_Hot') AND (OnLayer('Top Layer') OR OnLayer('Bottom Layer'))

Second Object: (InNetClass('Primary_LV')) AND (OnLayer('Top Layer') OR OnLayer('Bottom Layer'))

Will work for trace-trace, trace-poly and poly-poly but not pad-anything

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Thru pads are OnMultiLayer, add that to the layer query. Also, you can use OnOutside or (OnTopLayer OR OnBottomLayer) instead of naming those layers directly (which is more fragile: layers can be renamed in the layer stack manager).

So, try:

InNetClass('Primary_Hot') AND (OnOutside OR OnMultiLayer)

Likewise, for multilayer, you can set different clearances for inner and outer by adding a similar query but with OnMid instead of OnOutside, to both clauses.

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  • \$\begingroup\$ That worked so well. Thank you Tim!!! \$\endgroup\$
    – Gotta_Ask
    Dec 10, 2022 at 1:14
  • \$\begingroup\$ You're welcome! Don't forget to upvote and mark as answer. \$\endgroup\$ Dec 10, 2022 at 4:41

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