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I am tasked with designing a multistage amplifier (maximum 3 stages) for a course project. The project asks us to amplify a sinusoidal signal with an amplitude of 20mV and a frequency of 20kHz. The aim is to achieve maximum symmetry of the signal and to achieve the highest possible gain. Input-output phase is not of consideration. The topology may be DC or AC coupled. Vcc is +12V. Only CE and CC amps are allowed.

I have designed a common-emitter amplifier that has a gain of approximately -200 and I am happy with the gain. However, I observe significant clipping on the negative cycle of the output signal.

I know from my courses that to achieve maximum symmetrical swing, the Vc and Vce voltages should be at a certain level. However, what I want to achieve is to reduce the difference between the positive peak and the negative peak voltages at the output (relative to "center" of the signal). I know that in order to achieve this, I need to make my input signal smaller than 26mV. I have experimented by changing the input voltage to 10mV but I still observed significant asymmetry in terms of positive and negative peaks.

To lower my input signal, do you think that using a common-collector amplifier as first stage is viable? I know that the gain of a common-collector amplifier (at best) is unity and in practical terms is lower than unity, thus it attenuates the input signal to a degree. I am thinking of designing a common-collector amplifier with a NPN BJT as the first stage with a gain of apprixmately 0.1 so that the input signal will be attenuated to around 1-2mV.

Regarding that I need to create this circuit in lab environment, do you think a common-collector as first stage is viable or should I lower the input voltage by simply using a basic voltage divider?

If utilizing a common-collector for this purpose is a good idea, what would be the shortcomings? If its a bad idea, why?

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    \$\begingroup\$ There are many constraints you appear to have over-looked. For instance, when designing an amplifier, it is important to specify the output load and the input impedance. In the absence of these numbers you can't justifiably get anywhere. Also, given that your specification is just for 20 kHz, you could used a highly tuned tank circuit to get really low distortion of the sinewave output but, it won't work particularly well at other frequencies. In short, much more detail needed. \$\endgroup\$
    – Andy aka
    Commented Dec 10, 2022 at 12:57
  • \$\begingroup\$ The output is meant to drive an 8 Ohm load. Thus, as the last stage I will definitely use a common-collector amplifer. The input source is either 600 Ohms or 50 Ohms. \$\endgroup\$ Commented Dec 10, 2022 at 13:01
  • \$\begingroup\$ @this_might_be_wrong Standard Class-A pair of BJTs (CC and CE arranged) and one more CE stage at the input. Bootstrap the output to the speaker to generate a constant current used to drive the output stage. That might be considered just two stages, not three, if the "output stage" can wrap up the entire class-A output pair. If so, then an even better design can be achieved using 4 BJTs in 3 stages. But given your writing of the question, I suspect it would take a lot of writing to teach what's needed to get across. \$\endgroup\$
    – jonk
    Commented Dec 11, 2022 at 6:26

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The project asks us to amplify a sinusoidal signal with an amplitude of 20mV and a frequency of 20kHz. The aim is to achieve maximum symmetry of the signal and to achieve the highest possible gain. Input-output phase is not of consideration. The topology may be DC or AC coupled. Vcc is +12V.
The output is meant to drive an 8 Ohm load.
The input source is either 600 Ohms or 50 Ohms.

This specification still seems incomplete. For example, the 8-ohm load with low distortion would suggest a loudspeaker. But the spec allows DC-coupling so the following circuit would meet the spec, but would be woefully inadequate for audio driving a loudspeaker:
woefully inadequate schematic

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  • \$\begingroup\$ I don't know. There's apparently a specification (must only use CE or CC amplifier stage) that's going to make it really hard to qualify a FET. Will have to get really creative, I think, to make that point stick. ;) Though a DC biased source seems to be allowed. \$\endgroup\$
    – jonk
    Commented Dec 11, 2022 at 6:13

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