What issues could multiple pull-up resistors with different sources cause for I2C?

Question

It seems pretty standard to place only 1 pair of pull-up resistors near the master chip, like shown in this diagram from a TI note on I2C.

But I've come across one circuit in my line of work that is incorrectly wired like this:

^{simulate this circuit – Schematic created using CircuitLab}

Both the slave and the master have their own set of pull-ups, with their own voltage sources. This does not work. But if you remove R4 and R3, everything works great... But why would those two extra resistors cause issues? Could it be some timing delay as the bus goes low or high on one end of the communication?

Unfortunately I can't post the entire schematic but the master chip is an MCU and the slave chip is a generic DAC with some registers. Neither chip have internal pull-up resistors.

Answer 1

Having two sets of pull-up resistors means the resistances are effectively in parallel. When both have the same value, the equivalent resistance is halved. Correspondingly, the current that each device's output element must sink is doubled.

Most likely, one or more of your devices can't sink enough current to pull the bus down below the logic low threshold. This should be observable on an oscilloscope.

I believe the original I2C specification required output drivers to be able to sink 3 mA of current. In your schematics with 3.3 V and two 2 kΩ resistors in parallel, the sink current is 3.3 mA, above the limit.

Answer 2

I2C is a slow transmission line. Terminating at both ends when rise time is far greater than the propagation ime delay [ns]. i.e. poor SNR results in poor communication error rates.

...

\$R_{OL}=V_{OL}/I_{OL}= 0.4~ V_{max}/ 3~ mA = 133 ~\Omega \$ -40 to 125 'C
\$ V_{IL}= 0.3 ~V_{DD} = 1 ~V\$

For two 1k pull-ups, using KVL in theory, \$V_{IL}=\dfrac{133 }{133+500}= 0.21 V_{DD}\$ which is less than \$0.3 V_{DD}\$ but supply DC-DC common mode (CM) noise degrades signal quality and performance, resulting in logic errors.

Reducing pullup by two shunts twice the stray noise but not if it is common mode.

Try STP or UTP cable and compare signal quality or remove 1k. Whichever looks better and meets spec will work.

Answer 3

The only downside is that the total resistance in parallel might be too low and too much current flows.

Depending on the MCU and the sensor, one or both of them may have outputs that are too weak to drive the total resistance. At least in the sense that the chip pulling the voltage down cannot pull the voltage low enough for the other chip to register that as logic low.

Better look at chip data sheets how much current they can safely handle. And better check if the voltages on the bus are within the specs of input logic levels of the chips.

Sure, the I2C specs defines these voltages and currents, but a component you can buy may be compatible with it or work in practice under some conditions, so the chips are not necessarily compliant with the specs.

Some chips have strong outputs that can drive the bus at 6mA specs. Some chips may have weaker outputs and can't even drive the required 3mA.

Your resistance values exceed the 3mA. It is also possible your MCU IO pins are incorrectly configured for driving the bus instead of the required open drain mode.

The bus will not generally be long enough to have the need to take time of flight of the signal into account, so two sets of pull-ups should not matter. So technically the schematics with dual pull-ups are not wrong, just the resistor values.

If the resistors are not connected to the same 3.3V supply, but for example two different 3.3V supply where the other supply can be turned off by the MCU, then it will be a completely different, larger problem.