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schematic

simulate this circuit – Schematic created using CircuitLab

I would like to know if it is possible to produce an n-channel jfet connected in fixed bias configuration with a high gain of 200. If so, can you please give me a part number or a circuit diagram? The criteria are as follows:

Amplifier type:FET n-channel
Configuration: Common source fixed biasing
frequency range:100Hz-1MHz
Input signal:35mV,Rs=2kohm
midband gain:200

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    \$\begingroup\$ Is this a homework assignment? A gain of 200 is kind of a lot for a single stage. I think it's possible to do, but will be hard with just a single JFET and a resistive load. \$\endgroup\$ – Bitrex Apr 6 '13 at 4:57
  • \$\begingroup\$ Thanx for replying. yes it's an assignment. i am using a 2N3821 transistor and the maximum gain am obtaining is just about 30.i don't know which variables i need to vary and which ones are constant from the equations of Av and gm. \$\endgroup\$ – Nadeem Choonee Apr 6 '13 at 7:10
  • \$\begingroup\$ Actually the assignment is a multistage amplifier where in the first stage there is a signal generator, the second is a small signal amplifier and the third is a power amplifier. \$\endgroup\$ – Nadeem Choonee Apr 6 '13 at 7:14
  • \$\begingroup\$ Click 'edit' on your question, hit Ctrl-M and draw the circuit diagram, so we know what you are writing about. \$\endgroup\$ – jippie Apr 6 '13 at 9:49
  • \$\begingroup\$ i'm not very sure if the circuit is actually correct and can be further implemented for a gain of 200. i simulated it on multisim and it seems that the max gain i can obtain is 30. \$\endgroup\$ – Nadeem Choonee Apr 6 '13 at 13:31
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I would like to know if it is possible to produce an n-channel jfet connected in fixed bias configuration with a high gain of 200.

For your circuit, the product of the small-signal transconductance and drain impedance at the operating point set an upper bound on the voltage gain.

Using the numbers @Andy aka provides:

\$A_v < 20k\Omega \times 6.5 \frac{mA}{V} = 130\$

Since your drain resistor and load are in parallel with the small-signal drain impedance, your circuit gain must be less than this upper bound.

So, as a first step, you must select a transistor with maximum possible voltage gain quite larger than 200.

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The forward-transconductance of the JFET defines how many amps flow through the drain for each volt you input to the gate. The 2N3819 it has a typical value of about 4000 but, according to the Fairchild data sheet this can be as low as 2000 or as high as 6500.

Using the 4000 figure, this translates to 4000 uA/volt or 4mA per volt. If you bias your amplifier appropriately for quiescent dc conditions and you apply a small input voltage to the gate of (say) 0.1V p-p, the drain current will move up and down by +0.2mA and -0.2mA from its nominal quiescent dc value. Because your circuit shows a 10k drain resistor, this current modulation converts to a voltage of 2Vp-p hence you have a gain of about 20.

But you see a gain of 30 and this means the transconductance is closer to the top figure of 6500.

Supposing you made the 10k drain resistor 100kohm - this would translate to a voltage gain of 200. This sounds OK but will it work at 1MHz? The answer is "no" because, the jfet has parasitic capacitances that will severely take advantage of such a high value resistor in the drain. The 2N3819 is quoted as having a reverse transfer capacitance (on the Fairchild data sheet) of 4pF and this will cause the amplifier to have a 3dB point at about 400kHz.

But, running the JFET at these extremes is really difficult in terms of board layout and interfacing. Imagine connecting your oscilloscope to the output - immediately you have added a few more pF and suddenly your bandwidth is 200kHz. However, this isn't the end of the story....

Output Conductance is quoted at 50 micro-siemens and when translated to output resistance this is 20k ohm. Here's another limiting factor - no point going much above 20k in the drain because the inherent slope of the drain voltage versus drain current is 20k ohms.

I'd like to see what simulation results predict for the 100k drain resistor - I'm just doing some simple math on numbers from a data sheet and there may well be other factors I haven't considered. I normally simulate so I'm a bit rusty on this type of exercise.

BF513 has a low capacitance of 0.3pF and a Gm of 7000 so maybe this is a better choice BUT... it has an output conductance of 90 uSiemen or 11k ohms.

You have to interface the output to a circuit that will add a "load". The load will likely hurt the circuit performance above 100kHz but the biggest problem I think you face is finding a JFET with an output conductance of less than 5 uSiemen (equiv. to 200kohm)

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In your criteria list, you say Rs=2K. If this is the series resistor (not shown in your schematic) in the source leg of the JFET, then the circuit will be biased OK, sort of. The output (drain) will be at ~10V DC. The gain will be dominated by the ratio of the load to source resistors, or 10k/2k = 5. The simple way of getting more gain (not sure that you can get >100) out of a single stage is to use two series resistors in the source leg to GND. The sum of the two will be 2k to keep the DC bias the same. The mid point of the resistors should have a cap to GND. The cap impedance at 30kHz should be low relative to the upper (gain setting) resistor. Suppose top resistor is 200 ohms and bottom is 1800. Then the gain is 50. 1uF might do.

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