# VHDL signals with initialized values

This is my code:

And this is the testbench:

I am a VHDL beginner, and now I am trying to understand how 'Process' works. I know that signals get the value only in the end of the process.

At t=0, the process starts because x changed, and x is in the sensitivity list.

So temp is getting 0 because x(2)=0, and x(1)=0. And y should get 0 because temp is 0 (not because the line above, but because the initial value that i gave him when I define the temp signal). And in the 'end process' line, y and temp get the values.

But in the simulation, y is on U state and I don't understand why.

The simulation:

Designs are synthesised and should not use initial values.

Testbenches are not synthesised and can safely use initial values. In your testbench, put an initial value of "000" onto the signal declaration for x thus:

  signal x     : std_logic_vector( 2 downto  0) := "000";


Next, change your design to eliminate temp. This solution could use a combinatorial statement (shown as Option 1) but you're trying to understand processes so use option 2.

  -- Process for: y  <=  x(2) xor x(1) xor (0).
process(x) is
variable temp   : std_logic;
begin
temp  :=  x(2) xor x(1);
y     <=  temp xor x(0);
end process;


It will now work as you wanted.

The problem in your original design and testbench is that the following simultaneously occur at simulation time 0 ns:

• x = "UUU" and it is scheduled to go to "000" in 1 simulation delta.
• Process is run on x = "UUU" value, so y <= temp xor x(0) produces y = '0' xor 'U' = 'U'.

After 10 ns, x goes to "001" and a new value is produced.

However, temp is being used like it's a variable in a software programming language, rather than a signal in VHDL that uses scheduled assignment within a process.

I have solved that part using a VHDL variable but I'd have preferred not to because I strongly recommend that new VHDL learners stay well away from variables until VHDL's operation of signals is thoroughly understood first. This is because VHDL variables are often misunderstood, sometimes seen as a process's 'local signals' or as 'nicer than signals because they are assigned to immediately'.

Variables were implemented in VHDL to serve a specific role, which is allowing intermediate nodes in a combinatorial logic circuit to be named and accessed. They have subsequent uses and virtues, particularly in simulation (faster simulation of RAM etc), but that's their root function in VHDL circuit designs. Misuse of VHDL variables can produce VHDL with different behaviour in simulation than in a synthesised circuit, which is the opposite of what simulation is supposed to be doing.

For your future VHDL circuit designs, this answer explains the benefits of using of reset circuit and the problems caused by initial values.

• Thank you for your answer. I did what you told me to do, but the simulation hasn't changed at all.
– idan
Commented Dec 15, 2022 at 8:41
• thank you very much. I just want to fully understand How process works. There is still something that doesnt understood. why x is on U state in the first running of the process? I made X get "000" in t=0 in the tb, and the process cannot begin if X is not changed because X is in the sensitivity list. so when the process in his first running, it has to be that X="000"
– idan
Commented Dec 15, 2022 at 9:22
• @idan, all processes are executed at time=0 so that their output signals are assigned a value. I have noted that your question is about learning how processes work so I've revised the answer for you to try, removing the combinatorial-only solution. Commented Dec 15, 2022 at 9:29
• So if I Understand you correcrly, that was my problem: when the simulation is starting, the process automatically runs and assumes that X="UUU", so because of that, temp is getting U and also y as well. and right after X is getting "000" and the process is starting again because X changed, and temp gets 0, but y is getting U because of the previous value of temp.
– idan
Commented Dec 15, 2022 at 9:48
• I think I understand it now. Thank you a lot.
– idan
Commented Dec 15, 2022 at 10:57