# Maximum number of slaves for a single SPI line

In my application, I have to connect a series of SPI sensors to a microcontroller, and I need to understand how many sensors I can connect on a single SPI interface of the MCU.

Searching on the internet, I understood that the maximum number of slaves that can be connected on a single SPI interface depends on the frequency of the clock. How exactly can I calculate this number? What datasheet parameters should I look for and what considerations should I make?

In my specific case it is an STM32 microcontroller and six or more MAX31856 sensors, but I would also like to understand how to generalize for other MCUs and sensors.

• Other important factors: trace/wire length, clock topology, sensitivity of slave to double clocking. Dec 15, 2022 at 10:30

It does not even depend on the frequency of clock that much. It depends on a lot of factors and it is difficult to calculate.

First of all you do have to know what SPI frequency each device supports, as that is the ultimate limit for the clock for each device.

Then, you need to know, how much data you need to transfer from each device and how often, to figure out if it is even possible in theory.

So a few thermocouple bytes read a few times per second from 6 chips is not a problem as chips support up to 5 MHz clock and you don't have to use the fastest possible clock.

Now, comes the hard part, the electronics that may impose further limits, or requires more hardware to make it work. Most important factor is, how far apart are the devices, will they be on same PCB or far apart.

The MCU and the sensors have electrical specs. MCU output has drive strength to drive a certain waveform into a certain load. The sensors are a load and require a certain waveform to work properly. More specifically, sensor requires that clock edges are fast enough, and the load is capacitive. The MCU can drive output edges with certain current and the more capacitive load there is the edges are slower. MCU and sensor datasheets mention what the waveforms need to be, and what waveforms can be expected with a certain load.

More capacitance comes from wiring between chips. So it is possible that MCU can drive the load of six sensors in theory, but due to additional load from wiring, the edges may become too slow.

If the SPI bus needs to travel outside a small device, it likely requires extra bus transceivers to work.

SPI by itself does not contain any built-in mechanism for dealing with multiple slaves on the same bus. (Like in I2C you have slave addresses to differentiate them). Typically SPI interface along with data lines (SCLK / SDI / SDO) includes 'chip select' pin (SS) which is used to enable the receiving slave. This can be leveraged effectively to switch between different slaves on the same bus.

So what essentially limits the number of devices connected is how many free GPIO pins you have available to connect to each slave's SS line. Or whatever other clever switching mechanism you might choose (like shift registers and so on)

• But the SS is the mechanism for dealing with multiple slaves on bus. And surely there are many other limitations, such as bus length and clock frequency, and how many chips can be driven by the bus before signals rise and fall too slowly. Not the pure amount of GPIO pins or switching mechanism to be able to select arbitratry amount of slave chips. Dec 15, 2022 at 10:40
• @Justme All these factors, like bus length and clock frequency and drive strength, are up to you, not up to SPI, so SPI wouldn't possibly be able to predict them. (MISO drive strength is not up to you, but up to the designer of the peripheral, but you can still make a circuit to amplify it) Dec 15, 2022 at 10:50
• @user253751 True, SPI does not define these things. But in practice, the answer to the original question is simply not that it's limited by the amount of free GPIO pins. If you need to transfer 1 megabit per chip from 10 chips then if chips have a 5 megabit limit then you can't do what you need to do with 1 bus. That is a limitation not up to me or you, that is the limit of the peripheral chip which can't be fixed except by using enough SPI buses. Dec 15, 2022 at 11:06
• @Justme while it is true that SS pin is part of SPI interface, a master device still typically only has one SS pin. So it is up to software/hardware designer to implement the device switching using GPIO or other resources outside of SPI scope. That's why I say that it is not included in the SPI itself. And while bus length, shielding and clock frequency are important factors, they only limit the speed/bandwidth, not the number of slaves directly. Dec 15, 2022 at 11:08
• @floppydisk In my experience, a master device typically has zero SS pins, and GPIOs are always used. Dec 15, 2022 at 11:09

Connecting six SPI slaves to a SPI master is not really a problem. If you have connected six SPI slaves in daisy chain, then observe the delays in sending and receiving data from six slaves. You can only process one slave at the master at any time. Probably, clock speed is not a issue in this case as it can be done in MHz range. If you have connected slaves directly, each can be controlled with a chip select connected to master. Each slave can be dealt with separately. If you are using multiplexer to control which SPI slave is connected, calculate MUX switching time which is usually about 1 to 3 micro seconds and see how it affects timing of SPI communication of each slave with master. When calculating timing calculate time of sending and receiving bytes and switching time of any other components in between. Add atleast 40% delay clock cycles required for one SPI slave payload between possible timing constraints of SPI communication with each slave assuming you have the same amount of data you send and receive with each slave. If it differs, change accordingly.

The calculation for maximum number of slaves of a SPI master depends on how you have connected them to the master. In most cases, sending or receiving data to and from SPI slaves at highest clock speed is not important. With lower clock speed and delay clock cycles for SPI communication interleaved with each slave, you can reduce your CPU load considerably. This becomes relevant if you are using a RTOS.

• While some chips can be daisy-chained, these can't. Dec 15, 2022 at 15:20
• Yes, thats true. Dec 15, 2022 at 17:50