Many FPGAs have phase-locked loops which can multiply the frequency of a clock. The signal path of a PLL is rather simple:

Phase detector -> Averaging Filter (LPF) -> Oscillator

Where the oscillator is fed back to the phase detector.

The PLL circuits have a minimum frequency requirement for the clock. The requirement is often high, in the several MHz range. I am wondering how crucial satisfying the requirement is, and where it is derived from.


  • Technically, what causes the minimum requirement?
  • How far out of spec (clock frequency below the requirement) would the PLL still be expected to function, and what does the possible error look like?

1 Answer 1


There are actually two minimum frequencies associated with an FPGA PLL. The first revision of this answer only addressed the first one, which is the minimum frequency of the VCO itself. The technical requirement here comes from the oscillator design, which is made entirely with on-chip components. Low frequencies require larger components, and the vast majority of users don't need low frequencies, or can derive them from higher ones. Violating this specification means that the PLL won't lock reliably (or at all), giving you an output frequency other than the one you expect.

The second requirement is a minimum frequency for the phase detector inputs. This frequency also appears at the output of the phase detetor. The technical requirement for this is related to the bandwidth of the low-pass filter between the phase detector and the VCO. If this specification is violated — the frequency is too low — then there will be too much frequency modulation of the VCO output.

  • \$\begingroup\$ Which component in specific becomes larger with lower frequency? Is it considered good practice to use a faster clock to "boost" the clock to the PLL range (there will obviously be some jitter)? \$\endgroup\$
    – techmann
    Commented Dec 16, 2022 at 1:13
  • \$\begingroup\$ @techmann "boost" the clock to the PLL range: What? What do you mean by boosting? If you mean just using a faster clock source for the PLL then this just called using the PLL within specification. If you mean boosting a lower clock frequency into the PLL's valid input range then this is a Catch-22 because how did you boost the frequency without a PLL. \$\endgroup\$
    – DKNguyen
    Commented Dec 16, 2022 at 4:33
  • \$\begingroup\$ @DKNguyen By boosting I mean that on each pos edge of the slow clock variable T is initialized to 1. Said variable then alternates every X ticks of the faster clock, thus producing a multiplied or "boosted" clock output T that is in phase but with some jitter. Would PLL produce correct output for such clock T? \$\endgroup\$
    – techmann
    Commented Dec 16, 2022 at 13:23
  • \$\begingroup\$ No, that wouldn't work at all well. If you need a low-frequency PLL in an FPGA, consider using either a pure-digital or a hybrid approach, as described here: Reconstructing Clock for Serial Signal \$\endgroup\$
    – Dave Tweed
    Commented Dec 16, 2022 at 16:06

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