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For a buck converter, the maximum switching frequency depends on the minimum ON time of the converter.

Can someone please explain what this minimum ON time is? Is it the minimum time required to turn ON the power MOSFET switch? If so, what determines this turn ON time? What factors does it depend on?

Any equation concerning this would be helpful.

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    \$\begingroup\$ the maximum switching frequency depends on minimum on time of the converter. That's a pretty bold statement! Could you cite a source? \$\endgroup\$ Dec 17, 2022 at 16:39
  • \$\begingroup\$ @StainlessSteelRat Look at any datasheet of a converter with a minimum-on-time or minimum-off-time architecture and it will have a graph of maximum switching frequency vs duty cycle. I'm not sure this is a statement that needs a source; it's pretty obvious, at least to me? \$\endgroup\$
    – Hearth
    Dec 17, 2022 at 17:22
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    \$\begingroup\$ Are you asking solely about the minimum on time for the IC, or are you asking for the minimum on time for the entire buck converter circuit? The other components in the buck converter should be selected to be able to function with the IC operating within its specifications, but it's possible the rest of the circuit requires a minimum on time from the controller which is longer than the minimum on time which the controller IC can produce. So, what information are you really looking for here? Are you looking for a number for a specific circuit (a circuit/components which you haven't supplied)? \$\endgroup\$
    – Makyen
    Dec 18, 2022 at 16:19

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The minimum on-time is usually specific to current-mode control and defines the shortest pulse the circuit can deliver. There are two contributors to this minimum on-time:

  1. propagation delay, \$t_{prop}\$: when the current-sense comparator detects that the current setpoint is met, it instructs the logic to turn the DRV pin low which will turn the MOSFET off. However, before this happens, the signal must propagate through all logic blocks and it takes a certain time depending on various factors (technology, bias currents etc.). A classical figure is 100-200 ns for PWM controllers.

  2. leading edge blanking time, \$t_{LEB}\$: a LEB circuit is inserted between the current sense pin and the current-sense comparator. Its role is to blind the comparator for a small duration time (usually 100-150 ns) when the DRV pin turns the MOSFET on. This is to avoid erratic tripping with parasitic signals brought by various contributors at turn on (gate current, sec. side diode recovery process in CCM, stray capacitance and so on). A LEB is thus a kind of active filter.

The minimum on-time is thus: \$t_{on,min} = t_{prop} + t_{LEB}\$. You can observe it on a breadboard if you connect the drive output directly to the drive pin: the circuit will try to shut off immediately but will deliver a minimum pulse width. The below circuit illustrates the role of these blocks in a PWM controller:

enter image description here

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The minimum on time isn't really determined by anything but your controller IC. It's just a function of how the specific controller you're using operates. It'll be specified in the datasheet.

The existence of a minimum on time (and/or a minimum off time, in some controllers) is forced by speed limitations of the internal circuitry. Regardless of the switch you use externally (if it even uses an external switch; monolithic converters are quite common these days), the timing and logic circuitry inside the controller needs to switch from one state to the other, and it can only go so fast. Low pulse widths require wider-bandwidth circuitry.

Separately, in buck converters and synchronous boost converters, having a minimum on time (and off time) also ensures that, outside of low-power modes, the converter will always switch every cycle for at least a short length of time. This keeps the bootstrap capacitor used for the high-side switch charged.

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what determines this turn on time

How much charge needs to be pumped into the FET gate to turn it on, divided by how much current the driver outputs:

\$ i = dq/dt \$ is valid for anything that can contain charge, like a capacitor, or a MOSFET gate. This one is more complicated than a capacitor, because of Miller effect, but that doesn't change the fact that to switch the MOSFET, an adequate charge must be put into the gate.

FET datasheets usually specify "total gate charge Qg" but be aware that it depends on Vgs and Vds, so two MOSFETs having Qg's specified at the same Vds and Vgs can be compared (the lower Qg one will switch faster) but this is not necessarily the case if they are specified at different Vds and Vgs. Likewise if you use lower values of Vgs and Vds, Qg will be lower in your application.

It will switch slower if the amount of inductance becomes cumbersome, especially in the gate.

Current delivered by the driver will usually not be constant across the output voltage range either.

what is this minimum on time?

No circuit can output an infinitely short pulse, whether it's a logic gate or a MOSFET driver. They all have a speed limit, and therefore a minimum output pulse time below which the output will begin to go in the other direction before it has reached the flat top level of the pulse, turning a nice rectangular pulse into something more like a triangle. So there is a minimum off-time limit imposed by the driver chip itself. It can't go faster and still output a clean pulse.

enter image description here

However the MOSFET also adds another constraint: if the FET turns off immediately after turning on, or even worse if it doesn't have time to turn on completely then turns off immediately, then it will incur switching losses but it will do almost no actual useful work.

In a DC-DC converter, the FET is only doing useful stuff when it is conducting current. In fact, in an ideal converter the FET would switch instantly, so it would always be either on or off, and never in-between, so there would be no switching losses.

Basically, when on-time is large relative to switching time, it's worth it to pay switching losses, then pass a good amount of energy through the FET. Otherwise, it is more efficient to avoid switching losses by not switching at all, and skip cycles or go to sleep instead, operating the DC-DC converter in discontinuous mode. This also saves the energy required to drive the gate.

DC-DC chips designers take this into account and will usually pick a minimum on-time value that is not necessarily related to the fastest pulse the driver can output, but rather something reasonable to keep the converter efficient.

There are other constraints, for example if the chip samples the current through the FET only while it is on, then this requires a bit of time, and it has to stay on for longer than that for it to work.

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  • \$\begingroup\$ As I understand it, discontinuous mode just fully uses the inductive energy on each cycle (inductor current reaches zero). In continuous mode the inductor current varies between a maximum and minimum value each cycle. With pulse cycle skipping, usually for very light loads, the converter does not drive the inductor on each transition of the PWM frequency, but waits until the output has dropped a bit further before giving a pulse. This effectively reduces the PWM frequency while giving a minimum ON time pulse, and allows lower duty cycle. \$\endgroup\$
    – PStechPaul
    Dec 17, 2022 at 20:16
  • \$\begingroup\$ Yes, that's the idea. On light loads, it is more efficient to use either discontinuous mode or bursts followed by sleep, this reduces switching losses, at the cost of higher output voltage ripple. \$\endgroup\$
    – bobflux
    Dec 17, 2022 at 21:45
  • \$\begingroup\$ +1. This answer could be improved by pointing out that "the minimum on time" (the width of the shortest pulse) is independent of and typically designed to be much longer than "the time required to turn on the power MOSFET switch ... turn ON time" (the rising edge of the output of the MOSFET). \$\endgroup\$
    – davidcary
    Dec 19, 2022 at 18:57
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For a synchronous buck converter or a converter operating in CCM, the output voltage and input voltage are defined by this equation: -

$$V_{OUT} = V_{IN}\times \text{duty cycle}$$

So, to achieve a low value of \$V_{OUT}\$ from a high value of \$V_{IN}\$, the duty cycle has to be very low. And, if the switching frequency is high, the on-period of the MOSFET has to be very short. The higher the operating frequency, the lower the time period in which the MOSFET is on.

Hence, you can only go so-far with this before the MOSFET isn't properly activated and, when that happens, output accuracy suffers.

Is it the minimum time required to turn on power MOSFET switch?

Yes.

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