PWM in H-Brigde for Low-Frequency Inverter

Question

I'm trying to make an H-bridge for a low-frequency inverter circuit using this reference implementation from Texas Instruments:

650-W Power Stage Without Heat Sink Ref Design or Low-Frequency Offline UPS (Rev. B)

But I'm having trouble in understanding the switching waveforms of the H-bridge.

Let's talk about the first half cycle of 10 ms, according to this reference, the FETs from the right side of the half-bridge are both switching at PWM frequency with complementary pulses, if this is true then we need to insert dead-time in every pulse of these signals to avoid any shoot-through condition.

Am I getting it right?

Any guidance would be greatly appreciated!

Answer 1

You are correct. Dead time is necessary to prevent shoot-through. The upper FET is switched on to provide a low resistance current path for the inductive current. This maintains the current. It bypasses the body diode. However the body diode will turn on during the dead time.