# Cannot trigger digital logic because half of source voltage is lost in impedance matching

I am using a 3.3V output of an NI controller over a coax transmission line. I have matched the termination resistor to the 50 Ohm source resistance. I need to use this output signal to control three different small circuits, so I need to buffer the signal and multiply/breakout to ensure sufficient current and to avoid further voltage drop.

simulate this circuit – Schematic created using CircuitLab

My problem is that 3.3V is spread across the source resistance and the termination resistance, so I am really only getting a 1.65V output signal, and this voltage is not high enough to trigger my digital logic chips. If I use a chip like the 74HC4050 buffer with Vcc=3.3V, its minimum high level input voltage is ~2.3V, so will not trigger high with my 1.65V signal.

I then looked at low voltage options like SN74LVC3G34, and at Vcc=3.3V that has a minimum high voltage input level of 2V, so this also won't work.

So in a 3.3V system, how do I use digital logic chips if I am losing half of my voltage due to impedance matching? I can't seem to trigger a high level on any digital chip that I've looked at.

• How fast and how often do you need to switch, and how long is the coax? In other words: does impedance matching the source really make sense here? Commented Dec 19, 2022 at 7:55
• I haven't been told the switching frequency to expect of the system, but I have been told that the digital chips may end up being too slow for the system. Wouldn't the rise time of the signal be set by the NI controller? The coax cable would be from 20-30cm.
– sion
Commented Dec 19, 2022 at 22:53

Impedance matching is commonly used for analog signals to maximize the power transfer. But this is not the goal for digital logic signals; you want the original voltage (without transmission line effects caused by reflections at places where the impedance changes).

A logic driver has a very low output impedance (usually lower than the line's characteristic impedance). A CMOS logic receiver typically has an extremly high impedance (for practical purposes, your RLx are infinite). There are many ways to terminate transmission lines to handle this; see, for example, page 15 of TI's AHC Logic Family application note:

See the app note for pros and cons of these methods.

In practice, source termination (series resistor at the source) is the most commonly used method, because a single resistor at the source is simple and cheap. Please note that the sum of the output impedance of the driver and the termination resistance should match the characteristic impedance of the line. (If you need to squeeze the highest speed out of your circuit, use AC termination, at the cost of higher power usage.)

In your case, the controller already has source termination. There is nothing else for you to do; just remove the other 50 Ω resistor.

Sometimes, terminating digital lines is required, sometimes not. If the rise time of the logic signal is at least 10x the round trip time of any cables/traces being driven, then termination is not required. Any wave propagation/reflection effects will be masked by the slow logic risetime.

When terminating digital transmission lines, the goal is to eliminate multiple transitions on the line. This only requires one end of the line terminated. There are two ways to do this

• series termination at the near end - where the transmission line feeds a single load
• shunt termination at the far end - where the transmission line has to feed loads spaced out along the line

Series termination is the cheapest on power. The sender has a series output termination, and launches a V/2 signal along the line. This propagates until it meets the open circuit at the end. The signal reflection at the open end causes the voltage there to jump up to V. The reflected wave travels back to the source, raising the line voltage to V, where it is absorbed in the termination.

As the line has a period when a V/2 signal is propagating down it, receivers cannot be put onto the line mid way, and expect to get a valid logic signal. This style only works for the load at the far end of the line.

Shunt termination has a driver either driving the line directly with V, or through a termination resistor with 2V (this latter option is of course not a standard logic gate), or driving a current into the line (like LVDS). Either way, it launches a signal of height V onto the line. This propagates to the end of the line, where it is absorbed in a shunt termination. A clean logic signal is available at all points along the line, so any number of high impedance logic receivers can use it.

Both If you are going between instruments with a doubly terminated coaxial line, you should not really be driving several gates in parallel with the output. You should receive the line with a suitable buffer, and then fan out to the gates. A differential line receiver is built to do this specific job.

In days gone by, the AM26C32 was very popular, but it's 5 V only operation. These days, something like the NB3N4666C would be its faster 3.3 V replacement. We try not to recommend particular devices, as they can become obsolete, but I think it's useful to have a real example to look at. Search for 'line receiver 3.3V' to find alternatives. Almost any LVDS to CMOS line receiver will also be able to do a similar job, but check the input voltage range. Set one input to 0.8 V to set the logic threshold, and connect the other to your line swinging between 0 and 1.65 V.

Some line receiver devices have schmidt inputs, some don't. They sharpen up a slow input risetime, and can offer a little bit of resilience to poor line termination. With a good driver, and a short doubly terminated coax line, they're unlikely to be needed.

• Series termination may not be the right solution for me if the line transitions to V/2 before V, seeing as I have three logic buffers on the line, not just one receiver right at the end. But it seems like the series resistor is built into the NI controller output. Power is not a big concern, this will be done in a lab environment. I have been told that I need to use the series terminator on the output and the shunt resistor on the end of the line, but was not given an explanation beyond that is the only way to eliminate reflections. Is that true? Are there other options available to me?
– sion
Commented Dec 22, 2022 at 0:18
• @sion If you must use series AND shunt termination (who said you must, professor, boss, regulatory authority, some random guy on the internet?) then your line will only go to 1/2 of driving voltage, so you must drive with 2x desired line voltage, or drive with a current like LVDS does. If you have multiple recievers, you must use shunt termination at the end, this suppresses reflections, there is NO NEED for series termination. If the series term is built into the driver, then you could group all your receivers to the far end of the line so they all see the single step of V. Commented Dec 22, 2022 at 6:10
• The direction to use both came from my manager. So if the 3.3V output is halved to 1.65V using both series and shunt, are there any digital logic buffers that will trigger high at that point, and output 3.3V? The best that I have seen has a minimum high input voltage of 2V. I could put all of the buffers right down the end of the line, as they'd all be on the same logic chip. There would still be a slight difference in their line lengths (distance between pins), which may still be a problem?
– sion
Commented Dec 22, 2022 at 22:16
• @sion it's time to take a step back and review the system design. What is the risetime of the source device? That controls whether you need to do anything exciting at all, and what devices you can use to buffer it. My answer above is mainly for devices within one board. However, if you use a long coax to get between instruments, you may well have to have dedicated devices to transmit and receive those signals. Usually, we would use one at each end, and then buffer the signal into the rest of the logic. An LVDS receiver could be pressed into service as a fast receive buffer to do that. Commented Dec 23, 2022 at 7:42
• If the data rate can tolerate it, you could reduce the risetime at the transmit buffer, which will make the lines electrically shorter. If the receive gates won't tolerate that increase in risetime, then a schmidt buffer will restore the fast risetime. You really need to fully specify what your system does to get a proper answer. Commented Dec 23, 2022 at 10:40

I do not know if this is the best solution, but in the end I had to add a line voltage level shifter chip to basically change the circuit from 3.3V logic to 5V logic. When the 5V logic is halved by the voltage divider created by the source and load termination resistors, it is halved to 2.5V, which is high enough for the 3.3V logic loads to recognise as logic high.

• It is a common solution, especially if rise times need to be very short or the loads are very far apart. Otherwise, I'd have source terminated it and simply put the loads close together (relative to the rise time). Commented Mar 15, 2023 at 1:34