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I'm trying to design a 4-layer development board which will have a MCU, GPS and a GPRS modules, etc. However I'm confused about whether the inner power layers should be full copper planes.
Should GND and VCC layers be full copper planes or only GND — or none of them? By the way, I'm thinking to distribute 3.3V on VCC layer only. I'm kind of a noob at that but I thought that if both VCC and GND would be full copper layer, there might occur a big capacitance.
Yes, using full planes (especially GND) is a good idea. This provides a lowest-impedance return path for your signals with no breaks. Further, the capacitive coupling between planes is desirable, which you will enhance further with additional bypass caps, placed carefully near your power pins.
Usually, a 4-layer stack-up looks like this:
The typical plane separators between L1/L2 and L3/L4 are thin, about 4-5 mil. This yields signal-to-plane trace impedances of about 60-70 ohms without impedance control using normal routing rules, and you can specify impedance control if needed.
The core spacing depends on your target finished board thickness. For a 0.065" thick board, the core will be most of the thickness, about 40 mils. If your board is thinner (e.g., 1mm) this core will be how this thickness is adjusted, while the L1/L2 + L3/L4 layer separators will stay the same.
Often the Power plane will be carved up into shapes to support multiple power domains. This is ok, so long as you ensure the shapes are properly bypassed, and that you don't have signals crossing over breaks between shapes.
Finally, if your signals do have to change reference planes, make sure there are bypasses nearby to provide an AC return path.
That said, your board has some RF stuff on it that may require clearances to the planes. Refer to the material for your modules and follow their layout guidelines.
The starting point is full copper planes. The GPS and GPRS modules will have external antennas, so the planes probably can be continuous under those modules as well. There's an option of cutting out the VCC plane under these modules only, to minimize coupling from VCC to the modules, should that be a problem.
