I am working on porting a large modern logic IC based PCB design to FPGA. It's a personal project, not work/professional or school homework. Just a learning exercise for myself.
Part of this design uses parallel EEPROMs as ROMs to take inputs on the address lines and perform operations based on the outputs (controlled by what's stored in ROM). Done to save chunks of glue logic on a PCB.
Using the Xilinx ROM Using Block RAM Resources (Verilog) I have made the ROMs and everything is fine. However, I notice that the ROMs have many patterns in them, and are just performing logic functions inside to generate the outputs.
My question is, will the Vivado toolchain work out that the BRAM functionality could be replaced with logic operations and create that instead, or will it always use the BRAMs?
The reason I ask is that on this design the MSB of each EEPROM is a reset control pin, which forces all outputs low. However this takes half of the ROM space (and thus a decent chunk of BRAM) just to contain all zeros. It's an easy win to half the ROM size and just handle the reset condition separately, doing so in the Verilog design. Other parts of the ROM contain large chunks of the same output for many given inputs, just by the nature of what's encoded into the ROMs.
Am I better to let the Vivado tooling do it's thing, or, make a Python script to pre-process the ROM binaries, and try to minimise the logic myself? Sticking with the ROMs maintains the original functionality & thus allows for new features/updates to easily be leveraged. But there are four 32kbit ROMs in the design, and that's tying up a lot of the BRAM resources in the small Artix7 35T part I'm using.
I'm competent with Verilog & hardware design, but not an expert. I can achieve working designs, albeit sometimes they're a bit naïve.