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I have seen a table of opcodes for RISC-V instructions (for base I 32 bit ISA). I am working with a RISC-V core on FPGA and had BRAM for instructions set to all zeros.

Does anybody know what happens when the RISC-V CPU gets an instruction as all zeros? Does it behave like an NOP?

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    \$\begingroup\$ You should be able to check what a disassembler has to say about it, at least. e.g. echo .word 0 > foo.s && clang -target riscv32 -c foo.s && llvm-objdump -d foo.o on my system disassembles it as two unimp unimplemented instructions. \$\endgroup\$ Dec 24, 2022 at 6:26

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This is not included other documents, but I found this quote from "Volume I: RISC-V Unprivileged ISA V20190608-Base-Ratified" quite interesting:

Encodings with bits [15:0] all zeros are defined as illegal instructions.

and

We consider it a feature that any length of instruction containing all zero bits is not legal, as this quickly traps erroneous jumps into zeroed memory regions. Similarly, we also reserve the instruction encoding containing all ones to be an illegal instruction, to catch the other common pattern observed with unprogrammed non-volatile memory devices, disconnected memory buses, or broken memory devices. Software can rely on a naturally aligned 32-bit word containing zero to act as an illegal instruction on all RISC-V implementations, to be used by software where an illegal instruction is explicitly desired.

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Does it behave like an NOP?

No. The all-zero word is simply an unknown instruction.

That makes it unspecified what a processor does here. It might simply "NOP" assuming the instruction is some unsupported exception.

However, when you read up on RISC-V profiles, it's, at least for application processors, strongly encouraged to raise an illegal exception instruction.

You're using a RISC-V core under your control; if documentation (or, honestly, code) doesn't specify what it does with all-0s, I'd assume it just crashes and burns in beautiful colors.

Whether I would implement all-zero decoding as NOP really depends on the use case – in some systems, being able to zero out memory and start the processor from just any position in the first half of memory to work itself through the NOPs until it hits my initialization code, might be helpful. In other systems, you'd basically hand software attackers a free ticket to the NOP slide amusement park, and screaming in anybody's face when you encounter an illegal instruction would be the right thing to do.

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  • \$\begingroup\$ In a debugger disassembly these are usually show as unimp \$\endgroup\$
    – Eugene Sh.
    Dec 22, 2022 at 22:17
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    \$\begingroup\$ There’s always ‘Halt and catch fire’! \$\endgroup\$
    – Kartman
    Dec 23, 2022 at 14:32

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