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For instance, let's assume a copper trace width of 10 mm on both sides of a double-layer FR4 board with a thickness of 1.5 mm, copper thickness 35 µm (1 ounce per square foot).

The traces are connected by one or many vias of an arbitrary diameter.

How much does the resistance or impedance of a via change if it gets completely filled with solder?

How much does this change depend on the diameter of the via or on the thickness of the PCB (better said on the layer thickness bridged by that particular via)?

My question originally aimed more on measured values but recently also mathematical contributions are welcome.

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  • \$\begingroup\$ You're probably better off look at the results of a PCB calculator because if you're in a situation where this matters, you're going to need to be calculating anyways. \$\endgroup\$
    – DKNguyen
    Dec 23, 2022 at 20:53
  • \$\begingroup\$ If you're using traces with a width of 10 mm, presumably you are concerned with current. Would bus bars soldered to the PCB be of interest to you? \$\endgroup\$ Dec 23, 2022 at 21:00
  • \$\begingroup\$ Yes, current is of interest, and no, I want to know if filling vias will improve conductivity - even if only a bit. \$\endgroup\$
    – datenheim
    Dec 23, 2022 at 21:46
  • \$\begingroup\$ Assuming your traces run (Bot&Top) run on-top of each other and are fed by an Source on Top and lead to a Sink on Top i would go with this configuration: Near your connections place enough vias so your Drill-Diameter -circumference is roughly 3* track width. This will provide a low-R connection between Top & Bottom. I would not fill these vias with solder as there can be issue with different thermal expansion factors and what not. \$\endgroup\$ Jan 4, 2023 at 16:45
  • \$\begingroup\$ You can also run only a single track on one layer and put "strips" of SMD-paste accross it. Adds only little extra cost in production, is realiable and increase your current rating drastically, as the reflowed soldern can be think (>>35um) \$\endgroup\$ Jan 4, 2023 at 16:46

3 Answers 3

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There are a lot of variables involved and I can't be bothered doing the math, so I did a practical test using a spare PCB I had made by OSHPARK. 1.6 mm board thickness, 1 oz copper, ENIG (gold) plating, 60/40 solder, 2 drill sizes:-

  • 0.33mm hole: no solder 0.5 mΩ, with solder 0.3 mΩ
  • 1.0mm hole: no solder 0.1 mΩ, with solder 0.075 mΩ

The resistance measurements are not very accurate because my meter only has a resolution of 0.1 mV, so even at 4 A (limit of my power supply) I only had single digits to work with. But you get the idea.

60/40 tin/lead solder has about 11% of the conductivity of copper. Pure tin is a little higher at 14%. However the copper plating in a via is not solid, so its resistance is also higher than pure copper.

Manufacturing variations may also be a concern. A via that tests fine may still have less plating thickness than normal, or a weak connection to the trace. Soldering through the via could make the connection more reliable at high current.

On the other hand, can you ensure that the solder goes through the hole properly? There is probably an optimum size that achieves best solder fill and most resistance reduction vs via area, but calculating it could be tricky.

Another consideration is how the current is routed though traces. If you need to go from one side of the board to the other then via resistance is obviously important, but if the current goes down both sides equally the vias do nothing and could even be counterproductive (since they reduce surface copper area).

I suggest finding the smallest via that fills reliably with solder, and put plenty of them in places where the current changes sides. Then test the voltage drop with and without solder. You may find that you don't need solder fill.

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    \$\begingroup\$ This answer is very useful and also provides some input to question 647419 \$\endgroup\$
    – datenheim
    Dec 24, 2022 at 10:52
  • \$\begingroup\$ I leave the question open for some time hoping someone else likes to report some more findings. \$\endgroup\$
    – datenheim
    Dec 27, 2022 at 18:17
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My rule of thumb on vias is 2 A per via... 10 mil via with a 22 mil pad and 1 ounce of copper plating in the hole... Increasing the plating in the hole gets a bit pricy and not all board houses are set up to do it.

As a side note, a Mechanical Engineer I worked with at Datron, Patrick Weber, did a white paper on thermal transfer of PTH vias in FR4 material.. I think he published his findings with IEEE or the Society of Mech Engineers.

Basically we found through trial and error that increasing the thickness of the copper plating in the holes or actually plating them solid copper was much more effective at thermal transfer and we found that SN63 solder was much less useful as a thermal conductor or an electrical conductor.

I usually use a 10 mil PTH (0.254 mm) because it still wicks up the solder if desired and seals the hole under a thermal pad, so that it doesn't retain contaminants that blow out in reflow soldering and it's easily created by most manufacturers and can be easily plated thru. For thermal pads under an IC or Transistor, I use an 8 mil hole with a 20 mil pad... At 14 mil diameter the solder may or may not wick into the hole. It's not that reliable.

As a rule, I usually fill all my vias with soldermask. So filling solder in vias is not a normal activity except under parts with thermal pads. I wouldn't depend on solder to get more current carrying capability as solder is not a great replacement for copper. If the copper trace gets too hot you might end up with solder flowing out of the hole dripping and contaminating the inside of your electronic assembly under extreme circumstances. So that might be a reliability issue as well.

I've experimented with silver epoxy too... messy... it depends on what you are trying to do of course. good luck. :)

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  • \$\begingroup\$ You wrote that SN63 was not very useful as thermal conductor. What solder worked better and how much better? Your comment of the solder filling getting liquid in extreme load cases is something really to keep in mind (but maybe if the board gets that hot one would also loose other components :) \$\endgroup\$
    – datenheim
    Jan 4, 2023 at 19:46
  • \$\begingroup\$ Is there a specific name for the feature of increased plating thickness within vias? \$\endgroup\$
    – datenheim
    Jan 4, 2023 at 19:50
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    \$\begingroup\$ If your board gets hot enough to melt solder, you are well beyond the temperature limit of FR4 and likely beyond the limit of any nearby components on the board. \$\endgroup\$
    – user4574
    Jan 5, 2023 at 2:17
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You can approximately estimate the resistance of a filled via by calculating the parallel resistance of a conductive cylinder (made of solder) and a conductive hollow cylinder (made of copper).

$$ R_{cu} = \frac{4*l*p_1}{\pi ((d+2t)^2 - d^2)} $$

$$ R_s = \frac{4*l*p_2}{\pi d^2 } $$

$$ R_{via} = \frac{R_{cu} * R_s}{R_{cu} + R_s} $$

enter image description here

  • t is the copper plating thickness in meters.
  • d is the via finished hole diameter in meters.
  • p1 is the resistivity of the copper plating Ω-m.
  • p2 is the resistivity of the solder fill in Ω-m.
  • l is the via length in meters.
  • Rcu is the copper resistance.
  • Rs is the solder resistance.
  • Rvia is the total resistance of the filled via.

Example1:
0.33mm finished hole diameter via with 1oz copper plating on a 1.6mm thick board filled with SnAgCu lead free solder.

$$ R_{cu} = \frac{4*1.6mm*17.4 nΩm}{\pi ((330um+2*35um)^2 - (330um)^2)} = 0.694mΩ$$

$$ R_s = \frac{4*1.6mm*120nΩm}{\pi (330um)^2 } = 2.24mΩ$$

$$ R_{via} = \frac{1.87mΩ * 3.78mΩ}{1.87mΩ + 3.78mΩ} = 0.529mΩ$$

So, the filled via is about 76% the resistance of the unfilled one.

Example2:

1mm finished hole diameter via with 1oz copper plating on a 1.6mm thick board filled with SnAgCu lead free solder.

$$ R_{cu} = \frac{4*1.6mm*17.4 nΩm}{\pi ((1mm+2*35um)^2 - (1mm)^2)} = 0.245mΩ$$

$$ R_s = \frac{4*1.6mm*120nΩm}{\pi (1mm)^2 } = 0.244mΩ$$

$$ R_{via} = \frac{1.87mΩ * 3.78mΩ}{1.87mΩ + 3.78mΩ} = 0.122mΩ$$

So, the filled via is about 50% the resistance of the unfilled one.

Note that even though the cross section of the solder fill is much larger than the cross section of the copper, its only having a minor effect due to the fact that the resistivity of the solder is like 7X higher.

There are other fillers (conductive epoxies) that you can use besides solder that may give much better results. There are also companies like NetVia Group that can fill the holes with solid copper if you wish.

Lastly, the resistance of the copper part is decreasing linearly with the reciprocal of the via diameter, but the resistance of the filled part is decreasing with the square of the reciprocal of the diameter. So the fill will have a lot more effect when using larger holes.

The fact that you are using a 10mm trace points to the possibility that your board is carrying 100A or more. Having done many boards like that, I would advise using lots of vias in a grid to avoid concentrating too much current in one place when making layer transitions. In some cases, I used as many as 20 filled vias when going from an inner layer into the pins of a high-power component. Also using multiple layers of 3-oz copper helps.

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  • \$\begingroup\$ "I used as many as 20 filled vias" - so, how and with what material and process have them been filled? Your calculation is IMO in good agreement with Bruce Abbots findings. Also interesting: lead free solders have >10% lower resistivity. \$\endgroup\$
    – datenheim
    Jan 5, 2023 at 15:16
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    \$\begingroup\$ @datenheim On higher current boards we have used NetVia Group as the PWB vendor, and they can fill the vias with solid copper using a plating process they developed for that. On other boards we would specify that an electrically conductive epoxy by used, but not the exact part number. Common fillers are DuPont CB100 or Tatsuto AE3030, both of which are like 100~200 times worse electrical conductors than copper but help with heat. allenwoodsgroup.com/pdf/TATSUTAAE3030.pdf \$\endgroup\$
    – user4574
    Jan 6, 2023 at 0:29

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